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1; RUN: llc -mtriple armv8a-none-linux-gnu -mattr=+dotprod -float-abi=hard < %s | FileCheck %s2 3declare <2 x i32> @llvm.arm.neon.udot.v2i32.v8i8(<2 x i32>, <8 x i8>, <8 x i8>)4declare <4 x i32> @llvm.arm.neon.udot.v4i32.v16i8(<4 x i32>, <16 x i8>, <16 x i8>)5declare <2 x i32> @llvm.arm.neon.sdot.v2i32.v8i8(<2 x i32>, <8 x i8>, <8 x i8>)6declare <4 x i32> @llvm.arm.neon.sdot.v4i32.v16i8(<4 x i32>, <16 x i8>, <16 x i8>)7 8define <2 x i32> @test_vdot_u32(<2 x i32> %a, <8 x i8> %b, <8 x i8> %c) #0 {9entry:10; CHECK-LABEL: test_vdot_u32:11; CHECK: vudot.u8 d0, d1, d212 %vdot1.i = call <2 x i32> @llvm.arm.neon.udot.v2i32.v8i8(<2 x i32> %a, <8 x i8> %b, <8 x i8> %c) #213 ret <2 x i32> %vdot1.i14}15 16define <4 x i32> @test_vdotq_u32(<4 x i32> %a, <16 x i8> %b, <16 x i8> %c) #0 {17entry:18; CHECK-LABEL: test_vdotq_u32:19; CHECK: vudot.u8 q0, q1, q220 %vdot1.i = call <4 x i32> @llvm.arm.neon.udot.v4i32.v16i8(<4 x i32> %a, <16 x i8> %b, <16 x i8> %c) #221 ret <4 x i32> %vdot1.i22}23 24define <2 x i32> @test_vdot_s32(<2 x i32> %a, <8 x i8> %b, <8 x i8> %c) #0 {25entry:26; CHECK-LABEL: test_vdot_s32:27; CHECK: vsdot.s8 d0, d1, d228 %vdot1.i = call <2 x i32> @llvm.arm.neon.sdot.v2i32.v8i8(<2 x i32> %a, <8 x i8> %b, <8 x i8> %c) #229 ret <2 x i32> %vdot1.i30}31 32define <4 x i32> @test_vdotq_s32(<4 x i32> %a, <16 x i8> %b, <16 x i8> %c) #0 {33entry:34; CHECK-LABEL: test_vdotq_s32:35; CHECK: vsdot.s8 q0, q1, q236 %vdot1.i = call <4 x i32> @llvm.arm.neon.sdot.v4i32.v16i8(<4 x i32> %a, <16 x i8> %b, <16 x i8> %c) #237 ret <4 x i32> %vdot1.i38}39 40define <2 x i32> @test_vdot_lane_u32(<2 x i32> %a, <8 x i8> %b, <8 x i8> %c) {41entry:42; CHECK-LABEL: test_vdot_lane_u32:43; CHECK: vudot.u8 d0, d1, d2[1]44 %.cast = bitcast <8 x i8> %c to <2 x i32>45 %shuffle = shufflevector <2 x i32> %.cast, <2 x i32> undef, <2 x i32> <i32 1, i32 1>46 %.cast5 = bitcast <2 x i32> %shuffle to <8 x i8>47 %vdot1.i = call <2 x i32> @llvm.arm.neon.udot.v2i32.v8i8(<2 x i32> %a, <8 x i8> %b, <8 x i8> %.cast5) #248 ret <2 x i32> %vdot1.i49}50 51define <4 x i32> @test_vdotq_lane_u32(<4 x i32> %a, <16 x i8> %b, <8 x i8> %c) {52entry:53; CHECK-LABEL: test_vdotq_lane_u32:54; CHECK: vudot.u8 q0, q1, d4[1]55 %.cast = bitcast <8 x i8> %c to <2 x i32>56 %shuffle = shufflevector <2 x i32> %.cast, <2 x i32> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>57 %.cast3 = bitcast <4 x i32> %shuffle to <16 x i8>58 %vdot1.i = call <4 x i32> @llvm.arm.neon.udot.v4i32.v16i8(<4 x i32> %a, <16 x i8> %b, <16 x i8> %.cast3) #259 ret <4 x i32> %vdot1.i60}61 62define <2 x i32> @test_vdot_lane_s32(<2 x i32> %a, <8 x i8> %b, <8 x i8> %c) {63entry:64; CHECK-LABEL: test_vdot_lane_s32:65; CHECK: vsdot.s8 d0, d1, d2[1]66 %.cast = bitcast <8 x i8> %c to <2 x i32>67 %shuffle = shufflevector <2 x i32> %.cast, <2 x i32> undef, <2 x i32> <i32 1, i32 1>68 %.cast5 = bitcast <2 x i32> %shuffle to <8 x i8>69 %vdot1.i = call <2 x i32> @llvm.arm.neon.sdot.v2i32.v8i8(<2 x i32> %a, <8 x i8> %b, <8 x i8> %.cast5) #270 ret <2 x i32> %vdot1.i71}72 73define <4 x i32> @test_vdotq_lane_s32(<4 x i32> %a, <16 x i8> %b, <8 x i8> %c) {74entry:75; CHECK-LABEL: test_vdotq_lane_s32:76; CHECK: vsdot.s8 q0, q1, d4[1]77 %.cast = bitcast <8 x i8> %c to <2 x i32>78 %shuffle = shufflevector <2 x i32> %.cast, <2 x i32> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>79 %.cast3 = bitcast <4 x i32> %shuffle to <16 x i8>80 %vdot1.i = call <4 x i32> @llvm.arm.neon.sdot.v4i32.v16i8(<4 x i32> %a, <16 x i8> %b, <16 x i8> %.cast3) #281 ret <4 x i32> %vdot1.i82}83