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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=armv8 -mattr=+v8.1a | FileCheck %s3 4;-----------------------------------------------------------------------------5; RDMA Vector6 7declare <4 x i16> @llvm.arm.neon.vqrdmulh.v4i16(<4 x i16>, <4 x i16>)8declare <8 x i16> @llvm.arm.neon.vqrdmulh.v8i16(<8 x i16>, <8 x i16>)9declare <2 x i32> @llvm.arm.neon.vqrdmulh.v2i32(<2 x i32>, <2 x i32>)10declare <4 x i32> @llvm.arm.neon.vqrdmulh.v4i32(<4 x i32>, <4 x i32>)11 12declare <4 x i16> @llvm.sadd.sat.v4i16(<4 x i16>, <4 x i16>)13declare <8 x i16> @llvm.sadd.sat.v8i16(<8 x i16>, <8 x i16>)14declare <2 x i32> @llvm.sadd.sat.v2i32(<2 x i32>, <2 x i32>)15declare <4 x i32> @llvm.sadd.sat.v4i32(<4 x i32>, <4 x i32>)16 17declare <4 x i16> @llvm.ssub.sat.v4i16(<4 x i16>, <4 x i16>)18declare <8 x i16> @llvm.ssub.sat.v8i16(<8 x i16>, <8 x i16>)19declare <2 x i32> @llvm.ssub.sat.v2i32(<2 x i32>, <2 x i32>)20declare <4 x i32> @llvm.ssub.sat.v4i32(<4 x i32>, <4 x i32>)21 22declare <4 x i16> @llvm.arm.neon.vqrdmlah.v4i16(<4 x i16>, <4 x i16>, <4 x i16>)23declare <2 x i32> @llvm.arm.neon.vqrdmlah.v2i32(<2 x i32>, <2 x i32>, <2 x i32>)24declare <8 x i16> @llvm.arm.neon.vqrdmlah.v8i16(<8 x i16>, <8 x i16>, <8 x i16>)25declare <4 x i32> @llvm.arm.neon.vqrdmlah.v4i32(<4 x i32>, <4 x i32>, <4 x i32>)26declare <4 x i16> @llvm.arm.neon.vqrdmlsh.v4i16(<4 x i16>, <4 x i16>, <4 x i16>)27declare <2 x i32> @llvm.arm.neon.vqrdmlsh.v2i32(<2 x i32>, <2 x i32>, <2 x i32>)28declare <8 x i16> @llvm.arm.neon.vqrdmlsh.v8i16(<8 x i16>, <8 x i16>, <8 x i16>)29declare <4 x i32> @llvm.arm.neon.vqrdmlsh.v4i32(<4 x i32>, <4 x i32>, <4 x i32>)30 31; The sadd intrinsics in this file previously transformed into sqrdmlah where they32; shouldn't. They should produce vqrdmulh and vadd.33 34define arm_aapcs_vfpcc <4 x i16> @test_vqrdmulah_v4i16(<4 x i16> %acc, <4 x i16> %mhs, <4 x i16> %rhs) {35; CHECK-LABEL: test_vqrdmulah_v4i16:36; CHECK: @ %bb.0:37; CHECK-NEXT: vqrdmulh.s16 d16, d1, d238; CHECK-NEXT: vqadd.s16 d0, d0, d1639; CHECK-NEXT: bx lr40 %prod = call <4 x i16> @llvm.arm.neon.vqrdmulh.v4i16(<4 x i16> %mhs, <4 x i16> %rhs)41 %retval = call <4 x i16> @llvm.sadd.sat.v4i16(<4 x i16> %acc, <4 x i16> %prod)42 ret <4 x i16> %retval43}44 45define arm_aapcs_vfpcc <8 x i16> @test_vqrdmulah_v8i16(<8 x i16> %acc, <8 x i16> %mhs, <8 x i16> %rhs) {46; CHECK-LABEL: test_vqrdmulah_v8i16:47; CHECK: @ %bb.0:48; CHECK-NEXT: vqrdmulh.s16 q8, q1, q249; CHECK-NEXT: vqadd.s16 q0, q0, q850; CHECK-NEXT: bx lr51 %prod = call <8 x i16> @llvm.arm.neon.vqrdmulh.v8i16(<8 x i16> %mhs, <8 x i16> %rhs)52 %retval = call <8 x i16> @llvm.sadd.sat.v8i16(<8 x i16> %acc, <8 x i16> %prod)53 ret <8 x i16> %retval54}55 56define arm_aapcs_vfpcc <2 x i32> @test_vqrdmulah_v2i32(<2 x i32> %acc, <2 x i32> %mhs, <2 x i32> %rhs) {57; CHECK-LABEL: test_vqrdmulah_v2i32:58; CHECK: @ %bb.0:59; CHECK-NEXT: vqrdmulh.s32 d16, d1, d260; CHECK-NEXT: vqadd.s32 d0, d0, d1661; CHECK-NEXT: bx lr62 %prod = call <2 x i32> @llvm.arm.neon.vqrdmulh.v2i32(<2 x i32> %mhs, <2 x i32> %rhs)63 %retval = call <2 x i32> @llvm.sadd.sat.v2i32(<2 x i32> %acc, <2 x i32> %prod)64 ret <2 x i32> %retval65}66 67define arm_aapcs_vfpcc <4 x i32> @test_vqrdmulah_v4i32(<4 x i32> %acc, <4 x i32> %mhs, <4 x i32> %rhs) {68; CHECK-LABEL: test_vqrdmulah_v4i32:69; CHECK: @ %bb.0:70; CHECK-NEXT: vqrdmulh.s32 q8, q1, q271; CHECK-NEXT: vqadd.s32 q0, q0, q872; CHECK-NEXT: bx lr73 %prod = call <4 x i32> @llvm.arm.neon.vqrdmulh.v4i32(<4 x i32> %mhs, <4 x i32> %rhs)74 %retval = call <4 x i32> @llvm.sadd.sat.v4i32(<4 x i32> %acc, <4 x i32> %prod)75 ret <4 x i32> %retval76}77 78define arm_aapcs_vfpcc <4 x i16> @test_vqrdmulsh_v4i16(<4 x i16> %acc, <4 x i16> %mhs, <4 x i16> %rhs) {79; CHECK-LABEL: test_vqrdmulsh_v4i16:80; CHECK: @ %bb.0:81; CHECK-NEXT: vqrdmulh.s16 d16, d1, d282; CHECK-NEXT: vqsub.s16 d0, d0, d1683; CHECK-NEXT: bx lr84 %prod = call <4 x i16> @llvm.arm.neon.vqrdmulh.v4i16(<4 x i16> %mhs, <4 x i16> %rhs)85 %retval = call <4 x i16> @llvm.ssub.sat.v4i16(<4 x i16> %acc, <4 x i16> %prod)86 ret <4 x i16> %retval87}88 89define arm_aapcs_vfpcc <8 x i16> @test_vqrdmulsh_v8i16(<8 x i16> %acc, <8 x i16> %mhs, <8 x i16> %rhs) {90; CHECK-LABEL: test_vqrdmulsh_v8i16:91; CHECK: @ %bb.0:92; CHECK-NEXT: vqrdmulh.s16 q8, q1, q293; CHECK-NEXT: vqsub.s16 q0, q0, q894; CHECK-NEXT: bx lr95 %prod = call <8 x i16> @llvm.arm.neon.vqrdmulh.v8i16(<8 x i16> %mhs, <8 x i16> %rhs)96 %retval = call <8 x i16> @llvm.ssub.sat.v8i16(<8 x i16> %acc, <8 x i16> %prod)97 ret <8 x i16> %retval98}99 100define arm_aapcs_vfpcc <2 x i32> @test_vqrdmulsh_v2i32(<2 x i32> %acc, <2 x i32> %mhs, <2 x i32> %rhs) {101; CHECK-LABEL: test_vqrdmulsh_v2i32:102; CHECK: @ %bb.0:103; CHECK-NEXT: vqrdmulh.s32 d16, d1, d2104; CHECK-NEXT: vqsub.s32 d0, d0, d16105; CHECK-NEXT: bx lr106 %prod = call <2 x i32> @llvm.arm.neon.vqrdmulh.v2i32(<2 x i32> %mhs, <2 x i32> %rhs)107 %retval = call <2 x i32> @llvm.ssub.sat.v2i32(<2 x i32> %acc, <2 x i32> %prod)108 ret <2 x i32> %retval109}110 111define arm_aapcs_vfpcc <4 x i32> @test_vqrdmulsh_v4i32(<4 x i32> %acc, <4 x i32> %mhs, <4 x i32> %rhs) {112; CHECK-LABEL: test_vqrdmulsh_v4i32:113; CHECK: @ %bb.0:114; CHECK-NEXT: vqrdmulh.s32 q8, q1, q2115; CHECK-NEXT: vqsub.s32 q0, q0, q8116; CHECK-NEXT: bx lr117 %prod = call <4 x i32> @llvm.arm.neon.vqrdmulh.v4i32(<4 x i32> %mhs, <4 x i32> %rhs)118 %retval = call <4 x i32> @llvm.ssub.sat.v4i32(<4 x i32> %acc, <4 x i32> %prod)119 ret <4 x i32> %retval120}121 122;-----------------------------------------------------------------------------123; RDMA Scalar124 125define arm_aapcs_vfpcc <4 x i16> @test_vqrdmulah_lane_s16(<4 x i16> %acc, <4 x i16> %x, <4 x i16> %v) {126; CHECK-LABEL: test_vqrdmulah_lane_s16:127; CHECK: @ %bb.0: @ %entry128; CHECK-NEXT: vqrdmulh.s16 d16, d1, d2[3]129; CHECK-NEXT: vqadd.s16 d0, d0, d16130; CHECK-NEXT: bx lr131entry:132 %shuffle = shufflevector <4 x i16> %v, <4 x i16> undef, <4 x i32> <i32 3, i32 3, i32 3, i32 3>133 %prod = call <4 x i16> @llvm.arm.neon.vqrdmulh.v4i16(<4 x i16> %x, <4 x i16> %shuffle)134 %retval = call <4 x i16> @llvm.sadd.sat.v4i16(<4 x i16> %acc, <4 x i16> %prod)135 ret <4 x i16> %retval136}137 138define arm_aapcs_vfpcc <8 x i16> @test_vqrdmulahq_lane_s16(<8 x i16> %acc, <8 x i16> %x, <4 x i16> %v) {139; CHECK-LABEL: test_vqrdmulahq_lane_s16:140; CHECK: @ %bb.0: @ %entry141; CHECK-NEXT: vqrdmulh.s16 q8, q1, d4[2]142; CHECK-NEXT: vqadd.s16 q0, q0, q8143; CHECK-NEXT: bx lr144entry:145 %shuffle = shufflevector <4 x i16> %v, <4 x i16> undef, <8 x i32> <i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2>146 %prod = call <8 x i16> @llvm.arm.neon.vqrdmulh.v8i16(<8 x i16> %x, <8 x i16> %shuffle)147 %retval = call <8 x i16> @llvm.sadd.sat.v8i16(<8 x i16> %acc, <8 x i16> %prod)148 ret <8 x i16> %retval149}150 151define arm_aapcs_vfpcc <2 x i32> @test_vqrdmulah_lane_s32(<2 x i32> %acc, <2 x i32> %x, <2 x i32> %v) {152; CHECK-LABEL: test_vqrdmulah_lane_s32:153; CHECK: @ %bb.0: @ %entry154; CHECK-NEXT: vqrdmulh.s32 d16, d1, d2[1]155; CHECK-NEXT: vqadd.s32 d0, d0, d16156; CHECK-NEXT: bx lr157entry:158 %shuffle = shufflevector <2 x i32> %v, <2 x i32> undef, <2 x i32> <i32 1, i32 1>159 %prod = tail call <2 x i32> @llvm.arm.neon.vqrdmulh.v2i32(<2 x i32> %x, <2 x i32> %shuffle)160 %retval = call <2 x i32> @llvm.sadd.sat.v2i32(<2 x i32> %acc, <2 x i32> %prod)161 ret <2 x i32> %retval162}163 164define arm_aapcs_vfpcc <4 x i32> @test_vqrdmulahq_lane_s32(<4 x i32> %acc,<4 x i32> %x, <2 x i32> %v) {165; CHECK-LABEL: test_vqrdmulahq_lane_s32:166; CHECK: @ %bb.0: @ %entry167; CHECK-NEXT: vqrdmulh.s32 q8, q1, d4[0]168; CHECK-NEXT: vqadd.s32 q0, q0, q8169; CHECK-NEXT: bx lr170entry:171 %shuffle = shufflevector <2 x i32> %v, <2 x i32> undef, <4 x i32> zeroinitializer172 %prod = tail call <4 x i32> @llvm.arm.neon.vqrdmulh.v4i32(<4 x i32> %x, <4 x i32> %shuffle)173 %retval = call <4 x i32> @llvm.sadd.sat.v4i32(<4 x i32> %acc, <4 x i32> %prod)174 ret <4 x i32> %retval175}176 177define arm_aapcs_vfpcc <4 x i16> @test_vqrdmulsh_lane_s16(<4 x i16> %acc, <4 x i16> %x, <4 x i16> %v) {178; CHECK-LABEL: test_vqrdmulsh_lane_s16:179; CHECK: @ %bb.0: @ %entry180; CHECK-NEXT: vqrdmulh.s16 d16, d1, d2[3]181; CHECK-NEXT: vqsub.s16 d0, d0, d16182; CHECK-NEXT: bx lr183entry:184 %shuffle = shufflevector <4 x i16> %v, <4 x i16> undef, <4 x i32> <i32 3, i32 3, i32 3, i32 3>185 %prod = call <4 x i16> @llvm.arm.neon.vqrdmulh.v4i16(<4 x i16> %x, <4 x i16> %shuffle)186 %retval = call <4 x i16> @llvm.ssub.sat.v4i16(<4 x i16> %acc, <4 x i16> %prod)187 ret <4 x i16> %retval188}189 190define arm_aapcs_vfpcc <8 x i16> @test_vqrdmulshq_lane_s16(<8 x i16> %acc, <8 x i16> %x, <4 x i16> %v) {191; CHECK-LABEL: test_vqrdmulshq_lane_s16:192; CHECK: @ %bb.0: @ %entry193; CHECK-NEXT: vqrdmulh.s16 q8, q1, d4[2]194; CHECK-NEXT: vqsub.s16 q0, q0, q8195; CHECK-NEXT: bx lr196entry:197 %shuffle = shufflevector <4 x i16> %v, <4 x i16> undef, <8 x i32> <i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2>198 %prod = call <8 x i16> @llvm.arm.neon.vqrdmulh.v8i16(<8 x i16> %x, <8 x i16> %shuffle)199 %retval = call <8 x i16> @llvm.ssub.sat.v8i16(<8 x i16> %acc, <8 x i16> %prod)200 ret <8 x i16> %retval201}202 203define arm_aapcs_vfpcc <2 x i32> @test_vqrdmulsh_lane_s32(<2 x i32> %acc, <2 x i32> %x, <2 x i32> %v) {204; CHECK-LABEL: test_vqrdmulsh_lane_s32:205; CHECK: @ %bb.0: @ %entry206; CHECK-NEXT: vqrdmulh.s32 d16, d1, d2[1]207; CHECK-NEXT: vqsub.s32 d0, d0, d16208; CHECK-NEXT: bx lr209entry:210 %shuffle = shufflevector <2 x i32> %v, <2 x i32> undef, <2 x i32> <i32 1, i32 1>211 %prod = tail call <2 x i32> @llvm.arm.neon.vqrdmulh.v2i32(<2 x i32> %x, <2 x i32> %shuffle)212 %retval = call <2 x i32> @llvm.ssub.sat.v2i32(<2 x i32> %acc, <2 x i32> %prod)213 ret <2 x i32> %retval214}215 216define arm_aapcs_vfpcc <4 x i32> @test_vqrdmulshq_lane_s32(<4 x i32> %acc,<4 x i32> %x, <2 x i32> %v) {217; CHECK-LABEL: test_vqrdmulshq_lane_s32:218; CHECK: @ %bb.0: @ %entry219; CHECK-NEXT: vqrdmulh.s32 q8, q1, d4[0]220; CHECK-NEXT: vqsub.s32 q0, q0, q8221; CHECK-NEXT: bx lr222entry:223 %shuffle = shufflevector <2 x i32> %v, <2 x i32> undef, <4 x i32> zeroinitializer224 %prod = tail call <4 x i32> @llvm.arm.neon.vqrdmulh.v4i32(<4 x i32> %x, <4 x i32> %shuffle)225 %retval = call <4 x i32> @llvm.ssub.sat.v4i32(<4 x i32> %acc, <4 x i32> %prod)226 ret <4 x i32> %retval227}228 229 230 231define arm_aapcs_vfpcc <4 x i16> @test_vqrdmlah_s16(<4 x i16> %a, <4 x i16> %b, <4 x i16> %c) {232; CHECK-LABEL: test_vqrdmlah_s16:233; CHECK: @ %bb.0: @ %entry234; CHECK-NEXT: vqrdmlah.s16 d0, d1, d2235; CHECK-NEXT: bx lr236entry:237 %vqrdmlah_v3.i = tail call <4 x i16> @llvm.arm.neon.vqrdmlah.v4i16(<4 x i16> %a, <4 x i16> %b, <4 x i16> %c) #3238 ret <4 x i16> %vqrdmlah_v3.i239}240 241define arm_aapcs_vfpcc <2 x i32> @test_vqrdmlah_s32(<2 x i32> %a, <2 x i32> %b, <2 x i32> %c) {242; CHECK-LABEL: test_vqrdmlah_s32:243; CHECK: @ %bb.0: @ %entry244; CHECK-NEXT: vqrdmlah.s32 d0, d1, d2245; CHECK-NEXT: bx lr246entry:247 %vqrdmlah_v3.i = tail call <2 x i32> @llvm.arm.neon.vqrdmlah.v2i32(<2 x i32> %a, <2 x i32> %b, <2 x i32> %c) #3248 ret <2 x i32> %vqrdmlah_v3.i249}250 251define arm_aapcs_vfpcc <8 x i16> @test_vqrdmlahq_s16(<8 x i16> %a, <8 x i16> %b, <8 x i16> %c) {252; CHECK-LABEL: test_vqrdmlahq_s16:253; CHECK: @ %bb.0: @ %entry254; CHECK-NEXT: vqrdmlah.s16 q0, q1, q2255; CHECK-NEXT: bx lr256entry:257 %vqrdmlahq_v3.i = tail call <8 x i16> @llvm.arm.neon.vqrdmlah.v8i16(<8 x i16> %a, <8 x i16> %b, <8 x i16> %c) #3258 ret <8 x i16> %vqrdmlahq_v3.i259}260 261define arm_aapcs_vfpcc <4 x i32> @test_vqrdmlahq_s32(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {262; CHECK-LABEL: test_vqrdmlahq_s32:263; CHECK: @ %bb.0: @ %entry264; CHECK-NEXT: vqrdmlah.s32 q0, q1, q2265; CHECK-NEXT: bx lr266entry:267 %vqrdmlahq_v3.i = tail call <4 x i32> @llvm.arm.neon.vqrdmlah.v4i32(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) #3268 ret <4 x i32> %vqrdmlahq_v3.i269}270 271define arm_aapcs_vfpcc <4 x i16> @test_vqrdmlah_lane_s16(<4 x i16> %a, <4 x i16> %b, <4 x i16> %c) {272; CHECK-LABEL: test_vqrdmlah_lane_s16:273; CHECK: @ %bb.0: @ %entry274; CHECK-NEXT: vqrdmlah.s16 d0, d1, d2[3]275; CHECK-NEXT: bx lr276entry:277 %lane = shufflevector <4 x i16> %c, <4 x i16> poison, <4 x i32> <i32 3, i32 3, i32 3, i32 3>278 %vqrdmlah_v3.i = tail call <4 x i16> @llvm.arm.neon.vqrdmlah.v4i16(<4 x i16> %a, <4 x i16> %b, <4 x i16> %lane) #3279 ret <4 x i16> %vqrdmlah_v3.i280}281 282define arm_aapcs_vfpcc <2 x i32> @test_vqrdmlah_lane_s32(<2 x i32> %a, <2 x i32> %b, <2 x i32> %c) {283; CHECK-LABEL: test_vqrdmlah_lane_s32:284; CHECK: @ %bb.0: @ %entry285; CHECK-NEXT: vqrdmlah.s32 d0, d1, d2[1]286; CHECK-NEXT: bx lr287entry:288 %lane = shufflevector <2 x i32> %c, <2 x i32> poison, <2 x i32> <i32 1, i32 1>289 %vqrdmlah_v3.i = tail call <2 x i32> @llvm.arm.neon.vqrdmlah.v2i32(<2 x i32> %a, <2 x i32> %b, <2 x i32> %lane) #3290 ret <2 x i32> %vqrdmlah_v3.i291}292 293define arm_aapcs_vfpcc <8 x i16> @test_vqrdmlahq_lane_s16(<8 x i16> %a, <8 x i16> %b, <4 x i16> %c) {294; CHECK-LABEL: test_vqrdmlahq_lane_s16:295; CHECK: @ %bb.0: @ %entry296; CHECK-NEXT: vqrdmlah.s16 q0, q1, d4[3]297; CHECK-NEXT: bx lr298entry:299 %lane = shufflevector <4 x i16> %c, <4 x i16> poison, <8 x i32> <i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3>300 %vqrdmlahq_v3.i = tail call <8 x i16> @llvm.arm.neon.vqrdmlah.v8i16(<8 x i16> %a, <8 x i16> %b, <8 x i16> %lane) #3301 ret <8 x i16> %vqrdmlahq_v3.i302}303 304define arm_aapcs_vfpcc <4 x i32> @test_vqrdmlahq_lane_s32(<4 x i32> %a, <4 x i32> %b, <2 x i32> %c) {305; CHECK-LABEL: test_vqrdmlahq_lane_s32:306; CHECK: @ %bb.0: @ %entry307; CHECK-NEXT: vqrdmlah.s32 q0, q1, d4[1]308; CHECK-NEXT: bx lr309entry:310 %lane = shufflevector <2 x i32> %c, <2 x i32> poison, <4 x i32> <i32 1, i32 1, i32 1, i32 1>311 %vqrdmlahq_v3.i = tail call <4 x i32> @llvm.arm.neon.vqrdmlah.v4i32(<4 x i32> %a, <4 x i32> %b, <4 x i32> %lane) #3312 ret <4 x i32> %vqrdmlahq_v3.i313}314 315define arm_aapcs_vfpcc <4 x i16> @test_vqrdmlsh_s16(<4 x i16> %a, <4 x i16> %b, <4 x i16> %c) {316; CHECK-LABEL: test_vqrdmlsh_s16:317; CHECK: @ %bb.0: @ %entry318; CHECK-NEXT: vqrdmlsh.s16 d0, d1, d2319; CHECK-NEXT: bx lr320entry:321 %vqrdmlsh_v3.i = tail call <4 x i16> @llvm.arm.neon.vqrdmlsh.v4i16(<4 x i16> %a, <4 x i16> %b, <4 x i16> %c) #3322 ret <4 x i16> %vqrdmlsh_v3.i323}324 325define arm_aapcs_vfpcc <2 x i32> @test_vqrdmlsh_s32(<2 x i32> %a, <2 x i32> %b, <2 x i32> %c) {326; CHECK-LABEL: test_vqrdmlsh_s32:327; CHECK: @ %bb.0: @ %entry328; CHECK-NEXT: vqrdmlsh.s32 d0, d1, d2329; CHECK-NEXT: bx lr330entry:331 %vqrdmlsh_v3.i = tail call <2 x i32> @llvm.arm.neon.vqrdmlsh.v2i32(<2 x i32> %a, <2 x i32> %b, <2 x i32> %c) #3332 ret <2 x i32> %vqrdmlsh_v3.i333}334 335define arm_aapcs_vfpcc <8 x i16> @test_vqrdmlshq_s16(<8 x i16> %a, <8 x i16> %b, <8 x i16> %c) {336; CHECK-LABEL: test_vqrdmlshq_s16:337; CHECK: @ %bb.0: @ %entry338; CHECK-NEXT: vqrdmlsh.s16 q0, q1, q2339; CHECK-NEXT: bx lr340entry:341 %vqrdmlshq_v3.i = tail call <8 x i16> @llvm.arm.neon.vqrdmlsh.v8i16(<8 x i16> %a, <8 x i16> %b, <8 x i16> %c) #3342 ret <8 x i16> %vqrdmlshq_v3.i343}344 345define arm_aapcs_vfpcc <4 x i32> @test_vqrdmlshq_s32(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {346; CHECK-LABEL: test_vqrdmlshq_s32:347; CHECK: @ %bb.0: @ %entry348; CHECK-NEXT: vqrdmlsh.s32 q0, q1, q2349; CHECK-NEXT: bx lr350entry:351 %vqrdmlshq_v3.i = tail call <4 x i32> @llvm.arm.neon.vqrdmlsh.v4i32(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) #3352 ret <4 x i32> %vqrdmlshq_v3.i353}354 355define arm_aapcs_vfpcc <4 x i16> @test_vqrdmlsh_lane_s16(<4 x i16> %a, <4 x i16> %b, <4 x i16> %c) {356; CHECK-LABEL: test_vqrdmlsh_lane_s16:357; CHECK: @ %bb.0: @ %entry358; CHECK-NEXT: vqrdmlsh.s16 d0, d1, d2[3]359; CHECK-NEXT: bx lr360entry:361 %lane = shufflevector <4 x i16> %c, <4 x i16> poison, <4 x i32> <i32 3, i32 3, i32 3, i32 3>362 %vqrdmlsh_v3.i = tail call <4 x i16> @llvm.arm.neon.vqrdmlsh.v4i16(<4 x i16> %a, <4 x i16> %b, <4 x i16> %lane) #3363 ret <4 x i16> %vqrdmlsh_v3.i364}365 366define arm_aapcs_vfpcc <2 x i32> @test_vqrdmlsh_lane_s32(<2 x i32> %a, <2 x i32> %b, <2 x i32> %c) {367; CHECK-LABEL: test_vqrdmlsh_lane_s32:368; CHECK: @ %bb.0: @ %entry369; CHECK-NEXT: vqrdmlsh.s32 d0, d1, d2[1]370; CHECK-NEXT: bx lr371entry:372 %lane = shufflevector <2 x i32> %c, <2 x i32> poison, <2 x i32> <i32 1, i32 1>373 %vqrdmlsh_v3.i = tail call <2 x i32> @llvm.arm.neon.vqrdmlsh.v2i32(<2 x i32> %a, <2 x i32> %b, <2 x i32> %lane) #3374 ret <2 x i32> %vqrdmlsh_v3.i375}376 377define arm_aapcs_vfpcc <8 x i16> @test_vqrdmlshq_lane_s16(<8 x i16> %a, <8 x i16> %b, <4 x i16> %c) {378; CHECK-LABEL: test_vqrdmlshq_lane_s16:379; CHECK: @ %bb.0: @ %entry380; CHECK-NEXT: vqrdmlsh.s16 q0, q1, d4[3]381; CHECK-NEXT: bx lr382entry:383 %lane = shufflevector <4 x i16> %c, <4 x i16> poison, <8 x i32> <i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3>384 %vqrdmlshq_v3.i = tail call <8 x i16> @llvm.arm.neon.vqrdmlsh.v8i16(<8 x i16> %a, <8 x i16> %b, <8 x i16> %lane) #3385 ret <8 x i16> %vqrdmlshq_v3.i386}387 388define arm_aapcs_vfpcc <4 x i32> @test_vqrdmlshq_lane_s32(<4 x i32> %a, <4 x i32> %b, <2 x i32> %c) {389; CHECK-LABEL: test_vqrdmlshq_lane_s32:390; CHECK: @ %bb.0: @ %entry391; CHECK-NEXT: vqrdmlsh.s32 q0, q1, d4[1]392; CHECK-NEXT: bx lr393entry:394 %lane = shufflevector <2 x i32> %c, <2 x i32> poison, <4 x i32> <i32 1, i32 1, i32 1, i32 1>395 %vqrdmlshq_v3.i = tail call <4 x i32> @llvm.arm.neon.vqrdmlsh.v4i32(<4 x i32> %a, <4 x i32> %b, <4 x i32> %lane) #3396 ret <4 x i32> %vqrdmlshq_v3.i397}398