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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=armv8-arm-none-eabi -verify-machineinstrs %s -o - | FileCheck %s3; RUN: llc -mtriple=armebv8-arm-none-eabi -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECKBE4 5; This is the same as Thumb2/mve-vmovn.ll, testing the same patterns for neon6; under both both LE and BE. The vmovn instruction is very different between7; mve and neon, so these tests are not necessarily expected to generate a (neon)8; vmovn.9 10define arm_aapcs_vfpcc <8 x i16> @vmovn32_trunc1(<4 x i32> %src1, <4 x i32> %src2) {11; CHECK-LABEL: vmovn32_trunc1:12; CHECK: @ %bb.0: @ %entry13; CHECK-NEXT: vzip.32 q0, q114; CHECK-NEXT: vmovn.i32 d17, q115; CHECK-NEXT: vmovn.i32 d16, q016; CHECK-NEXT: vorr q0, q8, q817; CHECK-NEXT: bx lr18;19; CHECKBE-LABEL: vmovn32_trunc1:20; CHECKBE: @ %bb.0: @ %entry21; CHECKBE-NEXT: vrev64.32 q8, q122; CHECKBE-NEXT: vrev64.32 q9, q023; CHECKBE-NEXT: vzip.32 q9, q824; CHECKBE-NEXT: vmovn.i32 d17, q825; CHECKBE-NEXT: vmovn.i32 d16, q926; CHECKBE-NEXT: vrev64.16 q0, q827; CHECKBE-NEXT: bx lr28entry:29 %strided.vec = shufflevector <4 x i32> %src1, <4 x i32> %src2, <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7>30 %out = trunc <8 x i32> %strided.vec to <8 x i16>31 ret <8 x i16> %out32}33 34define arm_aapcs_vfpcc <8 x i16> @vmovn32_trunc2(<4 x i32> %src1, <4 x i32> %src2) {35; CHECK-LABEL: vmovn32_trunc2:36; CHECK: @ %bb.0: @ %entry37; CHECK-NEXT: vzip.32 q1, q038; CHECK-NEXT: vmovn.i32 d1, q039; CHECK-NEXT: vmovn.i32 d0, q140; CHECK-NEXT: bx lr41;42; CHECKBE-LABEL: vmovn32_trunc2:43; CHECKBE: @ %bb.0: @ %entry44; CHECKBE-NEXT: vrev64.32 q8, q045; CHECKBE-NEXT: vrev64.32 q9, q146; CHECKBE-NEXT: vzip.32 q9, q847; CHECKBE-NEXT: vmovn.i32 d17, q848; CHECKBE-NEXT: vmovn.i32 d16, q949; CHECKBE-NEXT: vrev64.16 q0, q850; CHECKBE-NEXT: bx lr51entry:52 %strided.vec = shufflevector <4 x i32> %src1, <4 x i32> %src2, <8 x i32> <i32 4, i32 0, i32 5, i32 1, i32 6, i32 2, i32 7, i32 3>53 %out = trunc <8 x i32> %strided.vec to <8 x i16>54 ret <8 x i16> %out55}56 57define arm_aapcs_vfpcc <16 x i8> @vmovn16_trunc1(<8 x i16> %src1, <8 x i16> %src2) {58; CHECK-LABEL: vmovn16_trunc1:59; CHECK: @ %bb.0: @ %entry60; CHECK-NEXT: vzip.16 q0, q161; CHECK-NEXT: vmovn.i16 d17, q162; CHECK-NEXT: vmovn.i16 d16, q063; CHECK-NEXT: vorr q0, q8, q864; CHECK-NEXT: bx lr65;66; CHECKBE-LABEL: vmovn16_trunc1:67; CHECKBE: @ %bb.0: @ %entry68; CHECKBE-NEXT: vrev64.16 q8, q169; CHECKBE-NEXT: vrev64.16 q9, q070; CHECKBE-NEXT: vzip.16 q9, q871; CHECKBE-NEXT: vmovn.i16 d17, q872; CHECKBE-NEXT: vmovn.i16 d16, q973; CHECKBE-NEXT: vrev64.8 q0, q874; CHECKBE-NEXT: bx lr75entry:76 %strided.vec = shufflevector <8 x i16> %src1, <8 x i16> %src2, <16 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11, i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15>77 %out = trunc <16 x i16> %strided.vec to <16 x i8>78 ret <16 x i8> %out79}80 81define arm_aapcs_vfpcc <16 x i8> @vmovn16_trunc2(<8 x i16> %src1, <8 x i16> %src2) {82; CHECK-LABEL: vmovn16_trunc2:83; CHECK: @ %bb.0: @ %entry84; CHECK-NEXT: vzip.16 q1, q085; CHECK-NEXT: vmovn.i16 d1, q086; CHECK-NEXT: vmovn.i16 d0, q187; CHECK-NEXT: bx lr88;89; CHECKBE-LABEL: vmovn16_trunc2:90; CHECKBE: @ %bb.0: @ %entry91; CHECKBE-NEXT: vrev64.16 q8, q092; CHECKBE-NEXT: vrev64.16 q9, q193; CHECKBE-NEXT: vzip.16 q9, q894; CHECKBE-NEXT: vmovn.i16 d17, q895; CHECKBE-NEXT: vmovn.i16 d16, q996; CHECKBE-NEXT: vrev64.8 q0, q897; CHECKBE-NEXT: bx lr98entry:99 %strided.vec = shufflevector <8 x i16> %src1, <8 x i16> %src2, <16 x i32> <i32 8, i32 0, i32 9, i32 1, i32 10, i32 2, i32 11, i32 3, i32 12, i32 4, i32 13, i32 5, i32 14, i32 6, i32 15, i32 7>100 %out = trunc <16 x i16> %strided.vec to <16 x i8>101 ret <16 x i8> %out102}103 104 105define arm_aapcs_vfpcc <2 x i64> @vmovn64_t1(<2 x i64> %src1, <2 x i64> %src2) {106; CHECK-LABEL: vmovn64_t1:107; CHECK: @ %bb.0: @ %entry108; CHECK-NEXT: vmov.f64 d1, d2109; CHECK-NEXT: bx lr110;111; CHECKBE-LABEL: vmovn64_t1:112; CHECKBE: @ %bb.0: @ %entry113; CHECKBE-NEXT: vmov.f64 d1, d2114; CHECKBE-NEXT: bx lr115entry:116 %out = shufflevector <2 x i64> %src1, <2 x i64> %src2, <2 x i32> <i32 0, i32 2>117 ret <2 x i64> %out118}119 120define arm_aapcs_vfpcc <2 x i64> @vmovn64_t2(<2 x i64> %src1, <2 x i64> %src2) {121; CHECK-LABEL: vmovn64_t2:122; CHECK: @ %bb.0: @ %entry123; CHECK-NEXT: vorr d3, d0, d0124; CHECK-NEXT: vorr q0, q1, q1125; CHECK-NEXT: bx lr126;127; CHECKBE-LABEL: vmovn64_t2:128; CHECKBE: @ %bb.0: @ %entry129; CHECKBE-NEXT: vorr d3, d0, d0130; CHECKBE-NEXT: vorr q0, q1, q1131; CHECKBE-NEXT: bx lr132entry:133 %out = shufflevector <2 x i64> %src1, <2 x i64> %src2, <2 x i32> <i32 2, i32 0>134 ret <2 x i64> %out135}136 137define arm_aapcs_vfpcc <2 x i64> @vmovn64_b1(<2 x i64> %src1, <2 x i64> %src2) {138; CHECK-LABEL: vmovn64_b1:139; CHECK: @ %bb.0: @ %entry140; CHECK-NEXT: vmov.f64 d1, d3141; CHECK-NEXT: bx lr142;143; CHECKBE-LABEL: vmovn64_b1:144; CHECKBE: @ %bb.0: @ %entry145; CHECKBE-NEXT: vmov.f64 d1, d3146; CHECKBE-NEXT: bx lr147entry:148 %out = shufflevector <2 x i64> %src1, <2 x i64> %src2, <2 x i32> <i32 0, i32 3>149 ret <2 x i64> %out150}151 152define arm_aapcs_vfpcc <2 x i64> @vmovn64_b2(<2 x i64> %src1, <2 x i64> %src2) {153; CHECK-LABEL: vmovn64_b2:154; CHECK: @ %bb.0: @ %entry155; CHECK-NEXT: vmov.f64 d16, d3156; CHECK-NEXT: vorr d17, d0, d0157; CHECK-NEXT: vorr q0, q8, q8158; CHECK-NEXT: bx lr159;160; CHECKBE-LABEL: vmovn64_b2:161; CHECKBE: @ %bb.0: @ %entry162; CHECKBE-NEXT: vmov.f64 d16, d3163; CHECKBE-NEXT: vorr d17, d0, d0164; CHECKBE-NEXT: vorr q0, q8, q8165; CHECKBE-NEXT: bx lr166entry:167 %out = shufflevector <2 x i64> %src1, <2 x i64> %src2, <2 x i32> <i32 3, i32 0>168 ret <2 x i64> %out169}170 171define arm_aapcs_vfpcc <2 x i64> @vmovn64_b3(<2 x i64> %src1, <2 x i64> %src2) {172; CHECK-LABEL: vmovn64_b3:173; CHECK: @ %bb.0: @ %entry174; CHECK-NEXT: vmov.f64 d0, d1175; CHECK-NEXT: vmov.f64 d1, d2176; CHECK-NEXT: bx lr177;178; CHECKBE-LABEL: vmovn64_b3:179; CHECKBE: @ %bb.0: @ %entry180; CHECKBE-NEXT: vmov.f64 d0, d1181; CHECKBE-NEXT: vmov.f64 d1, d2182; CHECKBE-NEXT: bx lr183entry:184 %out = shufflevector <2 x i64> %src1, <2 x i64> %src2, <2 x i32> <i32 1, i32 2>185 ret <2 x i64> %out186}187 188define arm_aapcs_vfpcc <2 x i64> @vmovn64_b4(<2 x i64> %src1, <2 x i64> %src2) {189; CHECK-LABEL: vmovn64_b4:190; CHECK: @ %bb.0: @ %entry191; CHECK-NEXT: vorr d3, d1, d1192; CHECK-NEXT: vorr q0, q1, q1193; CHECK-NEXT: bx lr194;195; CHECKBE-LABEL: vmovn64_b4:196; CHECKBE: @ %bb.0: @ %entry197; CHECKBE-NEXT: vorr d3, d1, d1198; CHECKBE-NEXT: vorr q0, q1, q1199; CHECKBE-NEXT: bx lr200entry:201 %out = shufflevector <2 x i64> %src1, <2 x i64> %src2, <2 x i32> <i32 2, i32 1>202 ret <2 x i64> %out203}204 205 206 207define arm_aapcs_vfpcc <4 x i32> @vmovn32_t1(<4 x i32> %src1, <4 x i32> %src2) {208; CHECK-LABEL: vmovn32_t1:209; CHECK: @ %bb.0: @ %entry210; CHECK-NEXT: vtrn.32 q0, q1211; CHECK-NEXT: bx lr212;213; CHECKBE-LABEL: vmovn32_t1:214; CHECKBE: @ %bb.0: @ %entry215; CHECKBE-NEXT: vrev64.32 q8, q1216; CHECKBE-NEXT: vrev64.32 q9, q0217; CHECKBE-NEXT: vtrn.32 q9, q8218; CHECKBE-NEXT: vrev64.32 q0, q9219; CHECKBE-NEXT: bx lr220entry:221 %out = shufflevector <4 x i32> %src1, <4 x i32> %src2, <4 x i32> <i32 0, i32 4, i32 2, i32 6>222 ret <4 x i32> %out223}224 225define arm_aapcs_vfpcc <4 x i32> @vmovn32_t2(<4 x i32> %src1, <4 x i32> %src2) {226; CHECK-LABEL: vmovn32_t2:227; CHECK: @ %bb.0: @ %entry228; CHECK-NEXT: vtrn.32 q1, q0229; CHECK-NEXT: vorr q0, q1, q1230; CHECK-NEXT: bx lr231;232; CHECKBE-LABEL: vmovn32_t2:233; CHECKBE: @ %bb.0: @ %entry234; CHECKBE-NEXT: vrev64.32 q8, q0235; CHECKBE-NEXT: vrev64.32 q9, q1236; CHECKBE-NEXT: vtrn.32 q9, q8237; CHECKBE-NEXT: vrev64.32 q0, q9238; CHECKBE-NEXT: bx lr239entry:240 %out = shufflevector <4 x i32> %src1, <4 x i32> %src2, <4 x i32> <i32 4, i32 0, i32 6, i32 2>241 ret <4 x i32> %out242}243 244define arm_aapcs_vfpcc <4 x i32> @vmovn32_b1(<4 x i32> %src1, <4 x i32> %src2) {245; CHECK-LABEL: vmovn32_b1:246; CHECK: @ %bb.0: @ %entry247; CHECK-NEXT: vrev64.32 q8, q0248; CHECK-NEXT: vtrn.32 q8, q1249; CHECK-NEXT: vorr q0, q1, q1250; CHECK-NEXT: bx lr251;252; CHECKBE-LABEL: vmovn32_b1:253; CHECKBE: @ %bb.0: @ %entry254; CHECKBE-NEXT: vrev64.32 q8, q0255; CHECKBE-NEXT: vrev64.32 q9, q1256; CHECKBE-NEXT: vrev64.32 q8, q8257; CHECKBE-NEXT: vtrn.32 q8, q9258; CHECKBE-NEXT: vrev64.32 q0, q9259; CHECKBE-NEXT: bx lr260entry:261 %out = shufflevector <4 x i32> %src1, <4 x i32> %src2, <4 x i32> <i32 0, i32 5, i32 2, i32 7>262 ret <4 x i32> %out263}264 265define arm_aapcs_vfpcc <4 x i32> @vmovn32_b2(<4 x i32> %src1, <4 x i32> %src2) {266; CHECK-LABEL: vmovn32_b2:267; CHECK: @ %bb.0: @ %entry268; CHECK-NEXT: vext.32 q8, q0, q0, #1269; CHECK-NEXT: vtrn.32 q8, q1270; CHECK-NEXT: vext.32 q0, q1, q1, #1271; CHECK-NEXT: bx lr272;273; CHECKBE-LABEL: vmovn32_b2:274; CHECKBE: @ %bb.0: @ %entry275; CHECKBE-NEXT: vrev64.32 q8, q0276; CHECKBE-NEXT: vrev64.32 q9, q1277; CHECKBE-NEXT: vext.32 q8, q8, q8, #1278; CHECKBE-NEXT: vtrn.32 q8, q9279; CHECKBE-NEXT: vext.32 q8, q9, q9, #1280; CHECKBE-NEXT: vrev64.32 q0, q8281; CHECKBE-NEXT: bx lr282entry:283 %out = shufflevector <4 x i32> %src1, <4 x i32> %src2, <4 x i32> <i32 5, i32 0, i32 7, i32 2>284 ret <4 x i32> %out285}286 287define arm_aapcs_vfpcc <4 x i32> @vmovn32_b3(<4 x i32> %src1, <4 x i32> %src2) {288; CHECK-LABEL: vmovn32_b3:289; CHECK: @ %bb.0: @ %entry290; CHECK-NEXT: vorr q8, q0, q0291; CHECK-NEXT: vtrn.32 q8, q1292; CHECK-NEXT: vtrn.32 q0, q8293; CHECK-NEXT: vorr q0, q8, q8294; CHECK-NEXT: bx lr295;296; CHECKBE-LABEL: vmovn32_b3:297; CHECKBE: @ %bb.0: @ %entry298; CHECKBE-NEXT: vrev64.32 q9, q0299; CHECKBE-NEXT: vrev64.32 q8, q1300; CHECKBE-NEXT: vorr q10, q9, q9301; CHECKBE-NEXT: vtrn.32 q10, q8302; CHECKBE-NEXT: vtrn.32 q9, q10303; CHECKBE-NEXT: vrev64.32 q0, q10304; CHECKBE-NEXT: bx lr305entry:306 %out = shufflevector <4 x i32> %src1, <4 x i32> %src2, <4 x i32> <i32 1, i32 4, i32 3, i32 6>307 ret <4 x i32> %out308}309 310define arm_aapcs_vfpcc <4 x i32> @vmovn32_b4(<4 x i32> %src1, <4 x i32> %src2) {311; CHECK-LABEL: vmovn32_b4:312; CHECK: @ %bb.0: @ %entry313; CHECK-NEXT: vorr q8, q0, q0314; CHECK-NEXT: vtrn.32 q8, q1315; CHECK-NEXT: vtrn.32 q8, q0316; CHECK-NEXT: bx lr317;318; CHECKBE-LABEL: vmovn32_b4:319; CHECKBE: @ %bb.0: @ %entry320; CHECKBE-NEXT: vrev64.32 q9, q0321; CHECKBE-NEXT: vrev64.32 q8, q1322; CHECKBE-NEXT: vorr q10, q9, q9323; CHECKBE-NEXT: vtrn.32 q10, q8324; CHECKBE-NEXT: vtrn.32 q10, q9325; CHECKBE-NEXT: vrev64.32 q0, q9326; CHECKBE-NEXT: bx lr327entry:328 %out = shufflevector <4 x i32> %src1, <4 x i32> %src2, <4 x i32> <i32 4, i32 1, i32 6, i32 3>329 ret <4 x i32> %out330}331 332 333 334 335define arm_aapcs_vfpcc <8 x i16> @vmovn16_t1(<8 x i16> %src1, <8 x i16> %src2) {336; CHECK-LABEL: vmovn16_t1:337; CHECK: @ %bb.0: @ %entry338; CHECK-NEXT: vtrn.16 q0, q1339; CHECK-NEXT: bx lr340;341; CHECKBE-LABEL: vmovn16_t1:342; CHECKBE: @ %bb.0: @ %entry343; CHECKBE-NEXT: vrev64.16 q8, q1344; CHECKBE-NEXT: vrev64.16 q9, q0345; CHECKBE-NEXT: vtrn.16 q9, q8346; CHECKBE-NEXT: vrev64.16 q0, q9347; CHECKBE-NEXT: bx lr348entry:349 %out = shufflevector <8 x i16> %src1, <8 x i16> %src2, <8 x i32> <i32 0, i32 8, i32 2, i32 10, i32 4, i32 12, i32 6, i32 14>350 ret <8 x i16> %out351}352 353define arm_aapcs_vfpcc <8 x i16> @vmovn16_t2(<8 x i16> %src1, <8 x i16> %src2) {354; CHECK-LABEL: vmovn16_t2:355; CHECK: @ %bb.0: @ %entry356; CHECK-NEXT: vtrn.16 q1, q0357; CHECK-NEXT: vorr q0, q1, q1358; CHECK-NEXT: bx lr359;360; CHECKBE-LABEL: vmovn16_t2:361; CHECKBE: @ %bb.0: @ %entry362; CHECKBE-NEXT: vrev64.16 q8, q0363; CHECKBE-NEXT: vrev64.16 q9, q1364; CHECKBE-NEXT: vtrn.16 q9, q8365; CHECKBE-NEXT: vrev64.16 q0, q9366; CHECKBE-NEXT: bx lr367entry:368 %out = shufflevector <8 x i16> %src1, <8 x i16> %src2, <8 x i32> <i32 8, i32 0, i32 10, i32 2, i32 12, i32 4, i32 14, i32 6>369 ret <8 x i16> %out370}371 372define arm_aapcs_vfpcc <8 x i16> @vmovn16_b1(<8 x i16> %src1, <8 x i16> %src2) {373; CHECK-LABEL: vmovn16_b1:374; CHECK: @ %bb.0: @ %entry375; CHECK-NEXT: vrev32.16 d16, d1376; CHECK-NEXT: vrev32.16 d17, d0377; CHECK-NEXT: vtrn.16 d16, d3378; CHECK-NEXT: vtrn.16 d17, d2379; CHECK-NEXT: vorr q0, q1, q1380; CHECK-NEXT: bx lr381;382; CHECKBE-LABEL: vmovn16_b1:383; CHECKBE: @ %bb.0: @ %entry384; CHECKBE-NEXT: vrev64.16 d16, d1385; CHECKBE-NEXT: vrev64.16 d17, d0386; CHECKBE-NEXT: vrev64.16 d19, d3387; CHECKBE-NEXT: vrev32.16 d16, d16388; CHECKBE-NEXT: vrev64.16 d18, d2389; CHECKBE-NEXT: vrev32.16 d17, d17390; CHECKBE-NEXT: vtrn.16 d16, d19391; CHECKBE-NEXT: vtrn.16 d17, d18392; CHECKBE-NEXT: vrev64.16 q0, q9393; CHECKBE-NEXT: bx lr394entry:395 %out = shufflevector <8 x i16> %src1, <8 x i16> %src2, <8 x i32> <i32 0, i32 9, i32 2, i32 11, i32 4, i32 13, i32 6, i32 15>396 ret <8 x i16> %out397}398 399define arm_aapcs_vfpcc <8 x i16> @vmovn16_b2(<8 x i16> %src1, <8 x i16> %src2) {400; CHECK-LABEL: vmovn16_b2:401; CHECK: @ %bb.0: @ %entry402; CHECK-NEXT: vorr d17, d3, d3403; CHECK-NEXT: vtrn.16 d17, d1404; CHECK-NEXT: vorr d16, d2, d2405; CHECK-NEXT: vtrn.16 d16, d0406; CHECK-NEXT: vtrn.16 d3, d17407; CHECK-NEXT: vtrn.16 d2, d16408; CHECK-NEXT: vorr q0, q8, q8409; CHECK-NEXT: bx lr410;411; CHECKBE-LABEL: vmovn16_b2:412; CHECKBE: @ %bb.0: @ %entry413; CHECKBE-NEXT: vrev64.16 d17, d3414; CHECKBE-NEXT: vorr d21, d17, d17415; CHECKBE-NEXT: vrev64.16 d16, d1416; CHECKBE-NEXT: vrev64.16 d19, d2417; CHECKBE-NEXT: vrev64.16 d18, d0418; CHECKBE-NEXT: vtrn.16 d21, d16419; CHECKBE-NEXT: vorr d20, d19, d19420; CHECKBE-NEXT: vtrn.16 d20, d18421; CHECKBE-NEXT: vtrn.16 d17, d21422; CHECKBE-NEXT: vtrn.16 d19, d20423; CHECKBE-NEXT: vrev64.16 q0, q10424; CHECKBE-NEXT: bx lr425entry:426 %out = shufflevector <8 x i16> %src1, <8 x i16> %src2, <8 x i32> <i32 9, i32 0, i32 11, i32 2, i32 13, i32 4, i32 15, i32 6>427 ret <8 x i16> %out428}429 430define arm_aapcs_vfpcc <8 x i16> @vmovn16_b3(<8 x i16> %src1, <8 x i16> %src2) {431; CHECK-LABEL: vmovn16_b3:432; CHECK: @ %bb.0: @ %entry433; CHECK-NEXT: vorr d17, d1, d1434; CHECK-NEXT: vtrn.16 d17, d3435; CHECK-NEXT: vorr d16, d0, d0436; CHECK-NEXT: vtrn.16 d16, d2437; CHECK-NEXT: vtrn.16 d1, d17438; CHECK-NEXT: vtrn.16 d0, d16439; CHECK-NEXT: vorr q0, q8, q8440; CHECK-NEXT: bx lr441;442; CHECKBE-LABEL: vmovn16_b3:443; CHECKBE: @ %bb.0: @ %entry444; CHECKBE-NEXT: vrev64.16 d17, d1445; CHECKBE-NEXT: vorr d21, d17, d17446; CHECKBE-NEXT: vrev64.16 d16, d3447; CHECKBE-NEXT: vrev64.16 d19, d0448; CHECKBE-NEXT: vrev64.16 d18, d2449; CHECKBE-NEXT: vtrn.16 d21, d16450; CHECKBE-NEXT: vorr d20, d19, d19451; CHECKBE-NEXT: vtrn.16 d20, d18452; CHECKBE-NEXT: vtrn.16 d17, d21453; CHECKBE-NEXT: vtrn.16 d19, d20454; CHECKBE-NEXT: vrev64.16 q0, q10455; CHECKBE-NEXT: bx lr456entry:457 %out = shufflevector <8 x i16> %src1, <8 x i16> %src2, <8 x i32> <i32 1, i32 8, i32 3, i32 10, i32 5, i32 12, i32 7, i32 14>458 ret <8 x i16> %out459}460 461define arm_aapcs_vfpcc <8 x i16> @vmovn16_b4(<8 x i16> %src1, <8 x i16> %src2) {462; CHECK-LABEL: vmovn16_b4:463; CHECK: @ %bb.0: @ %entry464; CHECK-NEXT: vrev32.16 d16, d3465; CHECK-NEXT: vrev32.16 d17, d2466; CHECK-NEXT: vtrn.16 d16, d1467; CHECK-NEXT: vtrn.16 d17, d0468; CHECK-NEXT: bx lr469;470; CHECKBE-LABEL: vmovn16_b4:471; CHECKBE: @ %bb.0: @ %entry472; CHECKBE-NEXT: vrev64.16 d16, d3473; CHECKBE-NEXT: vrev64.16 d17, d2474; CHECKBE-NEXT: vrev64.16 d19, d1475; CHECKBE-NEXT: vrev32.16 d16, d16476; CHECKBE-NEXT: vrev64.16 d18, d0477; CHECKBE-NEXT: vrev32.16 d17, d17478; CHECKBE-NEXT: vtrn.16 d16, d19479; CHECKBE-NEXT: vtrn.16 d17, d18480; CHECKBE-NEXT: vrev64.16 q0, q9481; CHECKBE-NEXT: bx lr482entry:483 %out = shufflevector <8 x i16> %src1, <8 x i16> %src2, <8 x i32> <i32 8, i32 1, i32 10, i32 3, i32 12, i32 5, i32 14, i32 7>484 ret <8 x i16> %out485}486 487 488define arm_aapcs_vfpcc <16 x i8> @vmovn8_b1(<16 x i8> %src1, <16 x i8> %src2) {489; CHECK-LABEL: vmovn8_b1:490; CHECK: @ %bb.0: @ %entry491; CHECK-NEXT: vtrn.8 q0, q1492; CHECK-NEXT: bx lr493;494; CHECKBE-LABEL: vmovn8_b1:495; CHECKBE: @ %bb.0: @ %entry496; CHECKBE-NEXT: vrev64.8 q8, q1497; CHECKBE-NEXT: vrev64.8 q9, q0498; CHECKBE-NEXT: vtrn.8 q9, q8499; CHECKBE-NEXT: vrev64.8 q0, q9500; CHECKBE-NEXT: bx lr501entry:502 %out = shufflevector <16 x i8> %src1, <16 x i8> %src2, <16 x i32> <i32 0, i32 16, i32 2, i32 18, i32 4, i32 20, i32 6, i32 22, i32 8, i32 24, i32 10, i32 26, i32 12, i32 28, i32 14, i32 30>503 ret <16 x i8> %out504}505 506define arm_aapcs_vfpcc <16 x i8> @vmovn8_b2(<16 x i8> %src1, <16 x i8> %src2) {507; CHECK-LABEL: vmovn8_b2:508; CHECK: @ %bb.0: @ %entry509; CHECK-NEXT: vtrn.8 q1, q0510; CHECK-NEXT: vorr q0, q1, q1511; CHECK-NEXT: bx lr512;513; CHECKBE-LABEL: vmovn8_b2:514; CHECKBE: @ %bb.0: @ %entry515; CHECKBE-NEXT: vrev64.8 q8, q0516; CHECKBE-NEXT: vrev64.8 q9, q1517; CHECKBE-NEXT: vtrn.8 q9, q8518; CHECKBE-NEXT: vrev64.8 q0, q9519; CHECKBE-NEXT: bx lr520entry:521 %out = shufflevector <16 x i8> %src1, <16 x i8> %src2, <16 x i32> <i32 16, i32 0, i32 18, i32 2, i32 20, i32 4, i32 22, i32 6, i32 24, i32 8, i32 26, i32 10, i32 28, i32 12, i32 30, i32 14>522 ret <16 x i8> %out523}524 525define arm_aapcs_vfpcc <16 x i8> @vmovn8_t1(<16 x i8> %src1, <16 x i8> %src2) {526; CHECK-LABEL: vmovn8_t1:527; CHECK: @ %bb.0: @ %entry528; CHECK-NEXT: vorr q2, q0, q0529; CHECK-NEXT: vldr d16, .LCPI24_0530; CHECK-NEXT: vorr d6, d3, d3531; CHECK-NEXT: vtbl.8 d1, {d5, d6}, d16532; CHECK-NEXT: vorr d5, d2, d2533; CHECK-NEXT: vtbl.8 d0, {d4, d5}, d16534; CHECK-NEXT: bx lr535; CHECK-NEXT: .p2align 3536; CHECK-NEXT: @ %bb.1:537; CHECK-NEXT: .LCPI24_0:538; CHECK-NEXT: .byte 0 @ 0x0539; CHECK-NEXT: .byte 9 @ 0x9540; CHECK-NEXT: .byte 2 @ 0x2541; CHECK-NEXT: .byte 11 @ 0xb542; CHECK-NEXT: .byte 4 @ 0x4543; CHECK-NEXT: .byte 13 @ 0xd544; CHECK-NEXT: .byte 6 @ 0x6545; CHECK-NEXT: .byte 15 @ 0xf546;547; CHECKBE-LABEL: vmovn8_t1:548; CHECKBE: @ %bb.0: @ %entry549; CHECKBE-NEXT: vldr d16, .LCPI24_0550; CHECKBE-NEXT: vrev64.8 d19, d3551; CHECKBE-NEXT: vrev64.8 d21, d2552; CHECKBE-NEXT: vrev64.8 d18, d1553; CHECKBE-NEXT: vrev64.8 d16, d16554; CHECKBE-NEXT: vrev64.8 d20, d0555; CHECKBE-NEXT: vtbl.8 d19, {d18, d19}, d16556; CHECKBE-NEXT: vtbl.8 d18, {d20, d21}, d16557; CHECKBE-NEXT: vrev64.8 q0, q9558; CHECKBE-NEXT: bx lr559; CHECKBE-NEXT: .p2align 3560; CHECKBE-NEXT: @ %bb.1:561; CHECKBE-NEXT: .LCPI24_0:562; CHECKBE-NEXT: .byte 0 @ 0x0563; CHECKBE-NEXT: .byte 9 @ 0x9564; CHECKBE-NEXT: .byte 2 @ 0x2565; CHECKBE-NEXT: .byte 11 @ 0xb566; CHECKBE-NEXT: .byte 4 @ 0x4567; CHECKBE-NEXT: .byte 13 @ 0xd568; CHECKBE-NEXT: .byte 6 @ 0x6569; CHECKBE-NEXT: .byte 15 @ 0xf570entry:571 %out = shufflevector <16 x i8> %src1, <16 x i8> %src2, <16 x i32> <i32 0, i32 17, i32 2, i32 19, i32 4, i32 21, i32 6, i32 23, i32 8, i32 25, i32 10, i32 27, i32 12, i32 29, i32 14, i32 31>572 ret <16 x i8> %out573}574 575define arm_aapcs_vfpcc <16 x i8> @vmovn8_t2(<16 x i8> %src1, <16 x i8> %src2) {576; CHECK-LABEL: vmovn8_t2:577; CHECK: @ %bb.0: @ %entry578; CHECK-NEXT: @ kill: def $q1 killed $q1 def $d2_d3_d4579; CHECK-NEXT: vldr d18, .LCPI25_0580; CHECK-NEXT: vorr d4, d1, d1581; CHECK-NEXT: vtbl.8 d17, {d3, d4}, d18582; CHECK-NEXT: vorr d3, d0, d0583; CHECK-NEXT: vtbl.8 d16, {d2, d3}, d18584; CHECK-NEXT: vorr q0, q8, q8585; CHECK-NEXT: bx lr586; CHECK-NEXT: .p2align 3587; CHECK-NEXT: @ %bb.1:588; CHECK-NEXT: .LCPI25_0:589; CHECK-NEXT: .byte 1 @ 0x1590; CHECK-NEXT: .byte 8 @ 0x8591; CHECK-NEXT: .byte 3 @ 0x3592; CHECK-NEXT: .byte 10 @ 0xa593; CHECK-NEXT: .byte 5 @ 0x5594; CHECK-NEXT: .byte 12 @ 0xc595; CHECK-NEXT: .byte 7 @ 0x7596; CHECK-NEXT: .byte 14 @ 0xe597;598; CHECKBE-LABEL: vmovn8_t2:599; CHECKBE: @ %bb.0: @ %entry600; CHECKBE-NEXT: vldr d16, .LCPI25_0601; CHECKBE-NEXT: vrev64.8 d19, d1602; CHECKBE-NEXT: vrev64.8 d21, d0603; CHECKBE-NEXT: vrev64.8 d18, d3604; CHECKBE-NEXT: vrev64.8 d16, d16605; CHECKBE-NEXT: vrev64.8 d20, d2606; CHECKBE-NEXT: vtbl.8 d19, {d18, d19}, d16607; CHECKBE-NEXT: vtbl.8 d18, {d20, d21}, d16608; CHECKBE-NEXT: vrev64.8 q0, q9609; CHECKBE-NEXT: bx lr610; CHECKBE-NEXT: .p2align 3611; CHECKBE-NEXT: @ %bb.1:612; CHECKBE-NEXT: .LCPI25_0:613; CHECKBE-NEXT: .byte 1 @ 0x1614; CHECKBE-NEXT: .byte 8 @ 0x8615; CHECKBE-NEXT: .byte 3 @ 0x3616; CHECKBE-NEXT: .byte 10 @ 0xa617; CHECKBE-NEXT: .byte 5 @ 0x5618; CHECKBE-NEXT: .byte 12 @ 0xc619; CHECKBE-NEXT: .byte 7 @ 0x7620; CHECKBE-NEXT: .byte 14 @ 0xe621entry:622 %out = shufflevector <16 x i8> %src1, <16 x i8> %src2, <16 x i32> <i32 17, i32 0, i32 19, i32 2, i32 21, i32 4, i32 23, i32 6, i32 25, i32 8, i32 27, i32 10, i32 29, i32 12, i32 31, i32 14>623 ret <16 x i8> %out624}625 626define arm_aapcs_vfpcc <16 x i8> @vmovn8_t3(<16 x i8> %src1, <16 x i8> %src2) {627; CHECK-LABEL: vmovn8_t3:628; CHECK: @ %bb.0: @ %entry629; CHECK-NEXT: vorr q2, q0, q0630; CHECK-NEXT: vldr d16, .LCPI26_0631; CHECK-NEXT: vorr d6, d3, d3632; CHECK-NEXT: vtbl.8 d1, {d5, d6}, d16633; CHECK-NEXT: vorr d5, d2, d2634; CHECK-NEXT: vtbl.8 d0, {d4, d5}, d16635; CHECK-NEXT: bx lr636; CHECK-NEXT: .p2align 3637; CHECK-NEXT: @ %bb.1:638; CHECK-NEXT: .LCPI26_0:639; CHECK-NEXT: .byte 1 @ 0x1640; CHECK-NEXT: .byte 8 @ 0x8641; CHECK-NEXT: .byte 3 @ 0x3642; CHECK-NEXT: .byte 10 @ 0xa643; CHECK-NEXT: .byte 5 @ 0x5644; CHECK-NEXT: .byte 12 @ 0xc645; CHECK-NEXT: .byte 7 @ 0x7646; CHECK-NEXT: .byte 14 @ 0xe647;648; CHECKBE-LABEL: vmovn8_t3:649; CHECKBE: @ %bb.0: @ %entry650; CHECKBE-NEXT: vldr d16, .LCPI26_0651; CHECKBE-NEXT: vrev64.8 d19, d3652; CHECKBE-NEXT: vrev64.8 d21, d2653; CHECKBE-NEXT: vrev64.8 d18, d1654; CHECKBE-NEXT: vrev64.8 d16, d16655; CHECKBE-NEXT: vrev64.8 d20, d0656; CHECKBE-NEXT: vtbl.8 d19, {d18, d19}, d16657; CHECKBE-NEXT: vtbl.8 d18, {d20, d21}, d16658; CHECKBE-NEXT: vrev64.8 q0, q9659; CHECKBE-NEXT: bx lr660; CHECKBE-NEXT: .p2align 3661; CHECKBE-NEXT: @ %bb.1:662; CHECKBE-NEXT: .LCPI26_0:663; CHECKBE-NEXT: .byte 1 @ 0x1664; CHECKBE-NEXT: .byte 8 @ 0x8665; CHECKBE-NEXT: .byte 3 @ 0x3666; CHECKBE-NEXT: .byte 10 @ 0xa667; CHECKBE-NEXT: .byte 5 @ 0x5668; CHECKBE-NEXT: .byte 12 @ 0xc669; CHECKBE-NEXT: .byte 7 @ 0x7670; CHECKBE-NEXT: .byte 14 @ 0xe671entry:672 %out = shufflevector <16 x i8> %src1, <16 x i8> %src2, <16 x i32> <i32 1, i32 16, i32 3, i32 18, i32 5, i32 20, i32 7, i32 22, i32 9, i32 24, i32 11, i32 26, i32 13, i32 28, i32 15, i32 30>673 ret <16 x i8> %out674}675 676define arm_aapcs_vfpcc <16 x i8> @vmovn8_t4(<16 x i8> %src1, <16 x i8> %src2) {677; CHECK-LABEL: vmovn8_t4:678; CHECK: @ %bb.0: @ %entry679; CHECK-NEXT: @ kill: def $q1 killed $q1 def $d2_d3_d4680; CHECK-NEXT: vldr d18, .LCPI27_0681; CHECK-NEXT: vorr d4, d1, d1682; CHECK-NEXT: vtbl.8 d17, {d3, d4}, d18683; CHECK-NEXT: vorr d3, d0, d0684; CHECK-NEXT: vtbl.8 d16, {d2, d3}, d18685; CHECK-NEXT: vorr q0, q8, q8686; CHECK-NEXT: bx lr687; CHECK-NEXT: .p2align 3688; CHECK-NEXT: @ %bb.1:689; CHECK-NEXT: .LCPI27_0:690; CHECK-NEXT: .byte 0 @ 0x0691; CHECK-NEXT: .byte 9 @ 0x9692; CHECK-NEXT: .byte 2 @ 0x2693; CHECK-NEXT: .byte 11 @ 0xb694; CHECK-NEXT: .byte 4 @ 0x4695; CHECK-NEXT: .byte 13 @ 0xd696; CHECK-NEXT: .byte 6 @ 0x6697; CHECK-NEXT: .byte 15 @ 0xf698;699; CHECKBE-LABEL: vmovn8_t4:700; CHECKBE: @ %bb.0: @ %entry701; CHECKBE-NEXT: vldr d16, .LCPI27_0702; CHECKBE-NEXT: vrev64.8 d19, d1703; CHECKBE-NEXT: vrev64.8 d21, d0704; CHECKBE-NEXT: vrev64.8 d18, d3705; CHECKBE-NEXT: vrev64.8 d16, d16706; CHECKBE-NEXT: vrev64.8 d20, d2707; CHECKBE-NEXT: vtbl.8 d19, {d18, d19}, d16708; CHECKBE-NEXT: vtbl.8 d18, {d20, d21}, d16709; CHECKBE-NEXT: vrev64.8 q0, q9710; CHECKBE-NEXT: bx lr711; CHECKBE-NEXT: .p2align 3712; CHECKBE-NEXT: @ %bb.1:713; CHECKBE-NEXT: .LCPI27_0:714; CHECKBE-NEXT: .byte 0 @ 0x0715; CHECKBE-NEXT: .byte 9 @ 0x9716; CHECKBE-NEXT: .byte 2 @ 0x2717; CHECKBE-NEXT: .byte 11 @ 0xb718; CHECKBE-NEXT: .byte 4 @ 0x4719; CHECKBE-NEXT: .byte 13 @ 0xd720; CHECKBE-NEXT: .byte 6 @ 0x6721; CHECKBE-NEXT: .byte 15 @ 0xf722entry:723 %out = shufflevector <16 x i8> %src1, <16 x i8> %src2, <16 x i32> <i32 16, i32 1, i32 18, i32 3, i32 20, i32 5, i32 22, i32 7, i32 24, i32 9, i32 26, i32 11, i32 28, i32 13, i32 30, i32 15>724 ret <16 x i8> %out725}726 727define arm_aapcs_vfpcc <16 x i8> @test(<8 x i16> %src1, <8 x i16> %src2) {728; CHECK-LABEL: test:729; CHECK: @ %bb.0: @ %entry730; CHECK-NEXT: vtrn.8 q0, q1731; CHECK-NEXT: bx lr732;733; CHECKBE-LABEL: test:734; CHECKBE: @ %bb.0: @ %entry735; CHECKBE-NEXT: vrev64.16 q8, q1736; CHECKBE-NEXT: vrev64.16 q9, q0737; CHECKBE-NEXT: vtrn.8 q9, q8738; CHECKBE-NEXT: vrev64.8 q0, q9739; CHECKBE-NEXT: bx lr740entry:741 %a0 = extractelement <8 x i16> %src1, i32 0742 %a1 = extractelement <8 x i16> %src1, i32 1743 %a2 = extractelement <8 x i16> %src1, i32 2744 %a3 = extractelement <8 x i16> %src1, i32 3745 %a4 = extractelement <8 x i16> %src1, i32 4746 %a5 = extractelement <8 x i16> %src1, i32 5747 %a6 = extractelement <8 x i16> %src1, i32 6748 %a7 = extractelement <8 x i16> %src1, i32 7749 750 %b0 = extractelement <8 x i16> %src2, i32 0751 %b1 = extractelement <8 x i16> %src2, i32 1752 %b2 = extractelement <8 x i16> %src2, i32 2753 %b3 = extractelement <8 x i16> %src2, i32 3754 %b4 = extractelement <8 x i16> %src2, i32 4755 %b5 = extractelement <8 x i16> %src2, i32 5756 %b6 = extractelement <8 x i16> %src2, i32 6757 %b7 = extractelement <8 x i16> %src2, i32 7758 759 %s0 = trunc i16 %a0 to i8760 %s1 = trunc i16 %a1 to i8761 %s2 = trunc i16 %a2 to i8762 %s3 = trunc i16 %a3 to i8763 %s4 = trunc i16 %a4 to i8764 %s5 = trunc i16 %a5 to i8765 %s6 = trunc i16 %a6 to i8766 %s7 = trunc i16 %a7 to i8767 %t0 = trunc i16 %b0 to i8768 %t1 = trunc i16 %b1 to i8769 %t2 = trunc i16 %b2 to i8770 %t3 = trunc i16 %b3 to i8771 %t4 = trunc i16 %b4 to i8772 %t5 = trunc i16 %b5 to i8773 %t6 = trunc i16 %b6 to i8774 %t7 = trunc i16 %b7 to i8775 776 %r0 = insertelement <16 x i8> undef, i8 %s0, i32 0777 %r1 = insertelement <16 x i8> %r0, i8 %s1, i32 2778 %r2 = insertelement <16 x i8> %r1, i8 %s2, i32 4779 %r3 = insertelement <16 x i8> %r2, i8 %s3, i32 6780 %r4 = insertelement <16 x i8> %r3, i8 %s4, i32 8781 %r5 = insertelement <16 x i8> %r4, i8 %s5, i32 10782 %r6 = insertelement <16 x i8> %r5, i8 %s6, i32 12783 %r7 = insertelement <16 x i8> %r6, i8 %s7, i32 14784 %r10 = insertelement <16 x i8> %r7, i8 %t0, i32 1785 %r11 = insertelement <16 x i8> %r10, i8 %t1, i32 3786 %r12 = insertelement <16 x i8> %r11, i8 %t2, i32 5787 %r13 = insertelement <16 x i8> %r12, i8 %t3, i32 7788 %r14 = insertelement <16 x i8> %r13, i8 %t4, i32 9789 %r15 = insertelement <16 x i8> %r14, i8 %t5, i32 11790 %r16 = insertelement <16 x i8> %r15, i8 %t6, i32 13791 %r17 = insertelement <16 x i8> %r16, i8 %t7, i32 15792 793 ret <16 x i8> %r17794}795