331 lines · plain
1; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s2 3define <8 x i8> @vqadds8(ptr %A, ptr %B) nounwind {4;CHECK-LABEL: vqadds8:5;CHECK: vqadd.s86 %tmp1 = load <8 x i8>, ptr %A7 %tmp2 = load <8 x i8>, ptr %B8 %tmp3 = call <8 x i8> @llvm.arm.neon.vqadds.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)9 ret <8 x i8> %tmp310}11 12define <4 x i16> @vqadds16(ptr %A, ptr %B) nounwind {13;CHECK-LABEL: vqadds16:14;CHECK: vqadd.s1615 %tmp1 = load <4 x i16>, ptr %A16 %tmp2 = load <4 x i16>, ptr %B17 %tmp3 = call <4 x i16> @llvm.arm.neon.vqadds.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)18 ret <4 x i16> %tmp319}20 21define <2 x i32> @vqadds32(ptr %A, ptr %B) nounwind {22;CHECK-LABEL: vqadds32:23;CHECK: vqadd.s3224 %tmp1 = load <2 x i32>, ptr %A25 %tmp2 = load <2 x i32>, ptr %B26 %tmp3 = call <2 x i32> @llvm.arm.neon.vqadds.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)27 ret <2 x i32> %tmp328}29 30define <1 x i64> @vqadds64(ptr %A, ptr %B) nounwind {31;CHECK-LABEL: vqadds64:32;CHECK: vqadd.s6433 %tmp1 = load <1 x i64>, ptr %A34 %tmp2 = load <1 x i64>, ptr %B35 %tmp3 = call <1 x i64> @llvm.arm.neon.vqadds.v1i64(<1 x i64> %tmp1, <1 x i64> %tmp2)36 ret <1 x i64> %tmp337}38 39define <8 x i8> @vqaddu8(ptr %A, ptr %B) nounwind {40;CHECK-LABEL: vqaddu8:41;CHECK: vqadd.u842 %tmp1 = load <8 x i8>, ptr %A43 %tmp2 = load <8 x i8>, ptr %B44 %tmp3 = call <8 x i8> @llvm.arm.neon.vqaddu.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)45 ret <8 x i8> %tmp346}47 48define <4 x i16> @vqaddu16(ptr %A, ptr %B) nounwind {49;CHECK-LABEL: vqaddu16:50;CHECK: vqadd.u1651 %tmp1 = load <4 x i16>, ptr %A52 %tmp2 = load <4 x i16>, ptr %B53 %tmp3 = call <4 x i16> @llvm.arm.neon.vqaddu.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)54 ret <4 x i16> %tmp355}56 57define <2 x i32> @vqaddu32(ptr %A, ptr %B) nounwind {58;CHECK-LABEL: vqaddu32:59;CHECK: vqadd.u3260 %tmp1 = load <2 x i32>, ptr %A61 %tmp2 = load <2 x i32>, ptr %B62 %tmp3 = call <2 x i32> @llvm.arm.neon.vqaddu.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)63 ret <2 x i32> %tmp364}65 66define <1 x i64> @vqaddu64(ptr %A, ptr %B) nounwind {67;CHECK-LABEL: vqaddu64:68;CHECK: vqadd.u6469 %tmp1 = load <1 x i64>, ptr %A70 %tmp2 = load <1 x i64>, ptr %B71 %tmp3 = call <1 x i64> @llvm.arm.neon.vqaddu.v1i64(<1 x i64> %tmp1, <1 x i64> %tmp2)72 ret <1 x i64> %tmp373}74 75define <16 x i8> @vqaddQs8(ptr %A, ptr %B) nounwind {76;CHECK-LABEL: vqaddQs8:77;CHECK: vqadd.s878 %tmp1 = load <16 x i8>, ptr %A79 %tmp2 = load <16 x i8>, ptr %B80 %tmp3 = call <16 x i8> @llvm.arm.neon.vqadds.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)81 ret <16 x i8> %tmp382}83 84define <8 x i16> @vqaddQs16(ptr %A, ptr %B) nounwind {85;CHECK-LABEL: vqaddQs16:86;CHECK: vqadd.s1687 %tmp1 = load <8 x i16>, ptr %A88 %tmp2 = load <8 x i16>, ptr %B89 %tmp3 = call <8 x i16> @llvm.arm.neon.vqadds.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)90 ret <8 x i16> %tmp391}92 93define <4 x i32> @vqaddQs32(ptr %A, ptr %B) nounwind {94;CHECK-LABEL: vqaddQs32:95;CHECK: vqadd.s3296 %tmp1 = load <4 x i32>, ptr %A97 %tmp2 = load <4 x i32>, ptr %B98 %tmp3 = call <4 x i32> @llvm.arm.neon.vqadds.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)99 ret <4 x i32> %tmp3100}101 102define <2 x i64> @vqaddQs64(ptr %A, ptr %B) nounwind {103;CHECK-LABEL: vqaddQs64:104;CHECK: vqadd.s64105 %tmp1 = load <2 x i64>, ptr %A106 %tmp2 = load <2 x i64>, ptr %B107 %tmp3 = call <2 x i64> @llvm.arm.neon.vqadds.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2)108 ret <2 x i64> %tmp3109}110 111define <16 x i8> @vqaddQu8(ptr %A, ptr %B) nounwind {112;CHECK-LABEL: vqaddQu8:113;CHECK: vqadd.u8114 %tmp1 = load <16 x i8>, ptr %A115 %tmp2 = load <16 x i8>, ptr %B116 %tmp3 = call <16 x i8> @llvm.arm.neon.vqaddu.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)117 ret <16 x i8> %tmp3118}119 120define <8 x i16> @vqaddQu16(ptr %A, ptr %B) nounwind {121;CHECK-LABEL: vqaddQu16:122;CHECK: vqadd.u16123 %tmp1 = load <8 x i16>, ptr %A124 %tmp2 = load <8 x i16>, ptr %B125 %tmp3 = call <8 x i16> @llvm.arm.neon.vqaddu.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)126 ret <8 x i16> %tmp3127}128 129define <4 x i32> @vqaddQu32(ptr %A, ptr %B) nounwind {130;CHECK-LABEL: vqaddQu32:131;CHECK: vqadd.u32132 %tmp1 = load <4 x i32>, ptr %A133 %tmp2 = load <4 x i32>, ptr %B134 %tmp3 = call <4 x i32> @llvm.arm.neon.vqaddu.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)135 ret <4 x i32> %tmp3136}137 138define <2 x i64> @vqaddQu64(ptr %A, ptr %B) nounwind {139;CHECK-LABEL: vqaddQu64:140;CHECK: vqadd.u64141 %tmp1 = load <2 x i64>, ptr %A142 %tmp2 = load <2 x i64>, ptr %B143 %tmp3 = call <2 x i64> @llvm.arm.neon.vqaddu.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2)144 ret <2 x i64> %tmp3145}146 147 148define <8 x i8> @vqsubs8(ptr %A, ptr %B) nounwind {149;CHECK-LABEL: vqsubs8:150;CHECK: vqsub.s8151 %tmp1 = load <8 x i8>, ptr %A152 %tmp2 = load <8 x i8>, ptr %B153 %tmp3 = call <8 x i8> @llvm.arm.neon.vqsubs.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)154 ret <8 x i8> %tmp3155}156 157define <4 x i16> @vqsubs16(ptr %A, ptr %B) nounwind {158;CHECK-LABEL: vqsubs16:159;CHECK: vqsub.s16160 %tmp1 = load <4 x i16>, ptr %A161 %tmp2 = load <4 x i16>, ptr %B162 %tmp3 = call <4 x i16> @llvm.arm.neon.vqsubs.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)163 ret <4 x i16> %tmp3164}165 166define <2 x i32> @vqsubs32(ptr %A, ptr %B) nounwind {167;CHECK-LABEL: vqsubs32:168;CHECK: vqsub.s32169 %tmp1 = load <2 x i32>, ptr %A170 %tmp2 = load <2 x i32>, ptr %B171 %tmp3 = call <2 x i32> @llvm.arm.neon.vqsubs.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)172 ret <2 x i32> %tmp3173}174 175define <1 x i64> @vqsubs64(ptr %A, ptr %B) nounwind {176;CHECK-LABEL: vqsubs64:177;CHECK: vqsub.s64178 %tmp1 = load <1 x i64>, ptr %A179 %tmp2 = load <1 x i64>, ptr %B180 %tmp3 = call <1 x i64> @llvm.arm.neon.vqsubs.v1i64(<1 x i64> %tmp1, <1 x i64> %tmp2)181 ret <1 x i64> %tmp3182}183 184define <8 x i8> @vqsubu8(ptr %A, ptr %B) nounwind {185;CHECK-LABEL: vqsubu8:186;CHECK: vqsub.u8187 %tmp1 = load <8 x i8>, ptr %A188 %tmp2 = load <8 x i8>, ptr %B189 %tmp3 = call <8 x i8> @llvm.arm.neon.vqsubu.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)190 ret <8 x i8> %tmp3191}192 193define <4 x i16> @vqsubu16(ptr %A, ptr %B) nounwind {194;CHECK-LABEL: vqsubu16:195;CHECK: vqsub.u16196 %tmp1 = load <4 x i16>, ptr %A197 %tmp2 = load <4 x i16>, ptr %B198 %tmp3 = call <4 x i16> @llvm.arm.neon.vqsubu.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)199 ret <4 x i16> %tmp3200}201 202define <2 x i32> @vqsubu32(ptr %A, ptr %B) nounwind {203;CHECK-LABEL: vqsubu32:204;CHECK: vqsub.u32205 %tmp1 = load <2 x i32>, ptr %A206 %tmp2 = load <2 x i32>, ptr %B207 %tmp3 = call <2 x i32> @llvm.arm.neon.vqsubu.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)208 ret <2 x i32> %tmp3209}210 211define <1 x i64> @vqsubu64(ptr %A, ptr %B) nounwind {212;CHECK-LABEL: vqsubu64:213;CHECK: vqsub.u64214 %tmp1 = load <1 x i64>, ptr %A215 %tmp2 = load <1 x i64>, ptr %B216 %tmp3 = call <1 x i64> @llvm.arm.neon.vqsubu.v1i64(<1 x i64> %tmp1, <1 x i64> %tmp2)217 ret <1 x i64> %tmp3218}219 220define <16 x i8> @vqsubQs8(ptr %A, ptr %B) nounwind {221;CHECK-LABEL: vqsubQs8:222;CHECK: vqsub.s8223 %tmp1 = load <16 x i8>, ptr %A224 %tmp2 = load <16 x i8>, ptr %B225 %tmp3 = call <16 x i8> @llvm.arm.neon.vqsubs.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)226 ret <16 x i8> %tmp3227}228 229define <8 x i16> @vqsubQs16(ptr %A, ptr %B) nounwind {230;CHECK-LABEL: vqsubQs16:231;CHECK: vqsub.s16232 %tmp1 = load <8 x i16>, ptr %A233 %tmp2 = load <8 x i16>, ptr %B234 %tmp3 = call <8 x i16> @llvm.arm.neon.vqsubs.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)235 ret <8 x i16> %tmp3236}237 238define <4 x i32> @vqsubQs32(ptr %A, ptr %B) nounwind {239;CHECK-LABEL: vqsubQs32:240;CHECK: vqsub.s32241 %tmp1 = load <4 x i32>, ptr %A242 %tmp2 = load <4 x i32>, ptr %B243 %tmp3 = call <4 x i32> @llvm.arm.neon.vqsubs.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)244 ret <4 x i32> %tmp3245}246 247define <2 x i64> @vqsubQs64(ptr %A, ptr %B) nounwind {248;CHECK-LABEL: vqsubQs64:249;CHECK: vqsub.s64250 %tmp1 = load <2 x i64>, ptr %A251 %tmp2 = load <2 x i64>, ptr %B252 %tmp3 = call <2 x i64> @llvm.arm.neon.vqsubs.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2)253 ret <2 x i64> %tmp3254}255 256define <16 x i8> @vqsubQu8(ptr %A, ptr %B) nounwind {257;CHECK-LABEL: vqsubQu8:258;CHECK: vqsub.u8259 %tmp1 = load <16 x i8>, ptr %A260 %tmp2 = load <16 x i8>, ptr %B261 %tmp3 = call <16 x i8> @llvm.arm.neon.vqsubu.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)262 ret <16 x i8> %tmp3263}264 265define <8 x i16> @vqsubQu16(ptr %A, ptr %B) nounwind {266;CHECK-LABEL: vqsubQu16:267;CHECK: vqsub.u16268 %tmp1 = load <8 x i16>, ptr %A269 %tmp2 = load <8 x i16>, ptr %B270 %tmp3 = call <8 x i16> @llvm.arm.neon.vqsubu.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)271 ret <8 x i16> %tmp3272}273 274define <4 x i32> @vqsubQu32(ptr %A, ptr %B) nounwind {275;CHECK-LABEL: vqsubQu32:276;CHECK: vqsub.u32277 %tmp1 = load <4 x i32>, ptr %A278 %tmp2 = load <4 x i32>, ptr %B279 %tmp3 = call <4 x i32> @llvm.arm.neon.vqsubu.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)280 ret <4 x i32> %tmp3281}282 283define <2 x i64> @vqsubQu64(ptr %A, ptr %B) nounwind {284;CHECK-LABEL: vqsubQu64:285;CHECK: vqsub.u64286 %tmp1 = load <2 x i64>, ptr %A287 %tmp2 = load <2 x i64>, ptr %B288 %tmp3 = call <2 x i64> @llvm.arm.neon.vqsubu.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2)289 ret <2 x i64> %tmp3290}291 292declare <8 x i8> @llvm.arm.neon.vqadds.v8i8(<8 x i8>, <8 x i8>) nounwind readnone293declare <4 x i16> @llvm.arm.neon.vqadds.v4i16(<4 x i16>, <4 x i16>) nounwind readnone294declare <2 x i32> @llvm.arm.neon.vqadds.v2i32(<2 x i32>, <2 x i32>) nounwind readnone295declare <1 x i64> @llvm.arm.neon.vqadds.v1i64(<1 x i64>, <1 x i64>) nounwind readnone296 297declare <8 x i8> @llvm.arm.neon.vqaddu.v8i8(<8 x i8>, <8 x i8>) nounwind readnone298declare <4 x i16> @llvm.arm.neon.vqaddu.v4i16(<4 x i16>, <4 x i16>) nounwind readnone299declare <2 x i32> @llvm.arm.neon.vqaddu.v2i32(<2 x i32>, <2 x i32>) nounwind readnone300declare <1 x i64> @llvm.arm.neon.vqaddu.v1i64(<1 x i64>, <1 x i64>) nounwind readnone301 302declare <16 x i8> @llvm.arm.neon.vqadds.v16i8(<16 x i8>, <16 x i8>) nounwind readnone303declare <8 x i16> @llvm.arm.neon.vqadds.v8i16(<8 x i16>, <8 x i16>) nounwind readnone304declare <4 x i32> @llvm.arm.neon.vqadds.v4i32(<4 x i32>, <4 x i32>) nounwind readnone305declare <2 x i64> @llvm.arm.neon.vqadds.v2i64(<2 x i64>, <2 x i64>) nounwind readnone306 307declare <16 x i8> @llvm.arm.neon.vqaddu.v16i8(<16 x i8>, <16 x i8>) nounwind readnone308declare <8 x i16> @llvm.arm.neon.vqaddu.v8i16(<8 x i16>, <8 x i16>) nounwind readnone309declare <4 x i32> @llvm.arm.neon.vqaddu.v4i32(<4 x i32>, <4 x i32>) nounwind readnone310declare <2 x i64> @llvm.arm.neon.vqaddu.v2i64(<2 x i64>, <2 x i64>) nounwind readnone311 312declare <8 x i8> @llvm.arm.neon.vqsubs.v8i8(<8 x i8>, <8 x i8>) nounwind readnone313declare <4 x i16> @llvm.arm.neon.vqsubs.v4i16(<4 x i16>, <4 x i16>) nounwind readnone314declare <2 x i32> @llvm.arm.neon.vqsubs.v2i32(<2 x i32>, <2 x i32>) nounwind readnone315declare <1 x i64> @llvm.arm.neon.vqsubs.v1i64(<1 x i64>, <1 x i64>) nounwind readnone316 317declare <8 x i8> @llvm.arm.neon.vqsubu.v8i8(<8 x i8>, <8 x i8>) nounwind readnone318declare <4 x i16> @llvm.arm.neon.vqsubu.v4i16(<4 x i16>, <4 x i16>) nounwind readnone319declare <2 x i32> @llvm.arm.neon.vqsubu.v2i32(<2 x i32>, <2 x i32>) nounwind readnone320declare <1 x i64> @llvm.arm.neon.vqsubu.v1i64(<1 x i64>, <1 x i64>) nounwind readnone321 322declare <16 x i8> @llvm.arm.neon.vqsubs.v16i8(<16 x i8>, <16 x i8>) nounwind readnone323declare <8 x i16> @llvm.arm.neon.vqsubs.v8i16(<8 x i16>, <8 x i16>) nounwind readnone324declare <4 x i32> @llvm.arm.neon.vqsubs.v4i32(<4 x i32>, <4 x i32>) nounwind readnone325declare <2 x i64> @llvm.arm.neon.vqsubs.v2i64(<2 x i64>, <2 x i64>) nounwind readnone326 327declare <16 x i8> @llvm.arm.neon.vqsubu.v16i8(<16 x i8>, <16 x i8>) nounwind readnone328declare <8 x i16> @llvm.arm.neon.vqsubu.v8i16(<8 x i16>, <8 x i16>) nounwind readnone329declare <4 x i32> @llvm.arm.neon.vqsubu.v4i32(<4 x i32>, <4 x i32>) nounwind readnone330declare <2 x i64> @llvm.arm.neon.vqsubu.v2i64(<2 x i64>, <2 x i64>) nounwind readnone331