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1; RUN: llc -mtriple arm-eabi -mattr=+neon -disable-post-ra -pre-RA-sched source %s -o - | FileCheck %s2; RUN: llc -mtriple thumbv7-windows-itanium -mattr=+neon -disable-post-ra -pre-RA-sched source %s -o - | FileCheck %s3 4define <8 x i8> @sdivi8(ptr %A, ptr %B) nounwind {5 %tmp1 = load <8 x i8>, ptr %A6 %tmp2 = load <8 x i8>, ptr %B7 %tmp3 = sdiv <8 x i8> %tmp1, %tmp28 ret <8 x i8> %tmp39}10 11; CHECK-LABEL: sdivi8:12; CHECK: vrecpe.f3213; CHECK: vmovn.i3214; CHECK: vrecpe.f3215; CHECK: vmovn.i3216; CHECK: vmovn.i1617 18define <8 x i8> @udivi8(ptr %A, ptr %B) nounwind {19 %tmp1 = load <8 x i8>, ptr %A20 %tmp2 = load <8 x i8>, ptr %B21 %tmp3 = udiv <8 x i8> %tmp1, %tmp222 ret <8 x i8> %tmp323}24 25; CHECK-LABEL: udivi8:26; CHECK: vrecpe.f3227; CHECK: vrecps.f3228; CHECK: vmovn.i3229; CHECK: vrecpe.f3230; CHECK: vrecps.f3231; CHECK: vmovn.i3232; CHECK: vqmovun.s1633 34define <4 x i16> @sdivi16(ptr %A, ptr %B) nounwind {35 %tmp1 = load <4 x i16>, ptr %A36 %tmp2 = load <4 x i16>, ptr %B37 %tmp3 = sdiv <4 x i16> %tmp1, %tmp238 ret <4 x i16> %tmp339}40 41; CHECK-LABEL: sdivi16:42; CHECK: vrecpe.f3243; CHECK: vrecps.f3244; CHECK: vmovn.i3245 46define <4 x i16> @udivi16(ptr %A, ptr %B) nounwind {47 %tmp1 = load <4 x i16>, ptr %A48 %tmp2 = load <4 x i16>, ptr %B49 %tmp3 = udiv <4 x i16> %tmp1, %tmp250 ret <4 x i16> %tmp351}52 53; CHECK-LABEL: udivi16:54; CHECK: vrecpe.f3255; CHECK: vrecps.f3256; CHECK: vrecps.f3257; CHECK: vmovn.i3258 59