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1; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s2 3; PR12540: ARM backend lowering of FP_ROUND v2f64 to v2f32.4define <2 x float> @vtrunc(<2 x double> %a) {5; CHECK: vcvt.f32.f64 [[S0:s[0-9]+]], [[D0:d[0-9]+]]6; CHECK: vcvt.f32.f64 [[S1:s[0-9]+]], [[D1:d[0-9]+]]7 %vt = fptrunc <2 x double> %a to <2 x float>8 ret <2 x float> %vt9}10 11define <2 x double> @vextend(<2 x float> %a) {12; CHECK: vcvt.f64.f32 [[D0:d[0-9]+]], [[S0:s[0-9]+]]13; CHECK: vcvt.f64.f32 [[D1:d[0-9]+]], [[S1:s[0-9]+]]14 %ve = fpext <2 x float> %a to <2 x double>15 ret <2 x double> %ve16}17 18; We used to generate vmovs between scalar and vfp/neon registers.19; CHECK: vsitofp_double20define void @vsitofp_double(ptr %loadaddr,21 ptr %storeaddr) {22 %v0 = load <2 x i32>, ptr %loadaddr23; CHECK: vldr24; CHECK-NEXT: vcvt.f64.s3225; CHECK-NEXT: vcvt.f64.s3226; CHECK-NEXT: vst27 %r = sitofp <2 x i32> %v0 to <2 x double>28 store <2 x double> %r, ptr %storeaddr29 ret void30}31; CHECK: vuitofp_double32define void @vuitofp_double(ptr %loadaddr,33 ptr %storeaddr) {34 %v0 = load <2 x i32>, ptr %loadaddr35; CHECK: vldr36; CHECK-NEXT: vcvt.f64.u3237; CHECK-NEXT: vcvt.f64.u3238; CHECK-NEXT: vst39 %r = uitofp <2 x i32> %v0 to <2 x double>40 store <2 x double> %r, ptr %storeaddr41 ret void42}43