60 lines · plain
1; RUN: llc -mtriple=arm-eabi -float-abi=soft -mattr=+neon %s -o - | FileCheck %s2; RUN: llc -mtriple=arm-eabi -float-abi=soft -mcpu=swift %s -o - | FileCheck %s --check-prefix=SWIFT3 4; CHECK: t15; CHECK: vld1.646; CHECK: vld1.647; CHECK: vadd.i64 q8; CHECK: vst1.649; SWIFT: t110; SWIFT: vld1.64 {{.d[0-9]+, d[0-9]+}, \[r[0-9]+:128\]}}11; SWIFT: vld1.64 {{.d[0-9]+, d[0-9]+}, \[r[0-9]+:128\]}}12; SWIFT: vadd.i64 q13; SWIFT: vst1.64 {{.d[0-9]+, d[0-9]+}, \[r[0-9]+:128\]}}14define void @t1(ptr %r, ptr %a, ptr %b) nounwind {15entry:16 %0 = load <2 x i64>, ptr %a, align 16 ; <<2 x i64>> [#uses=1]17 %1 = load <2 x i64>, ptr %b, align 16 ; <<2 x i64>> [#uses=1]18 %2 = add <2 x i64> %0, %1 ; <<2 x i64>> [#uses=1]19 %3 = bitcast <2 x i64> %2 to <4 x i32> ; <<4 x i32>> [#uses=1]20 store <4 x i32> %3, ptr %r, align 1621 ret void22}23 24; CHECK: t225; CHECK: vld1.6426; CHECK: vld1.6427; CHECK: vsub.i64 q28; CHECK: vmov r0, r1, d29; CHECK: vmov r2, r3, d30; SWIFT: t231; SWIFT: vld1.64 {{.d[0-9]+, d[0-9]+}, \[r[0-9]+:128\]}}32; SWIFT: vld1.64 {{.d[0-9]+, d[0-9]+}, \[r[0-9]+:128\]}}33; SWIFT: vsub.i64 q34; SWIFT: vmov r0, r1, d35; SWIFT: vmov r2, r3, d36define <4 x i32> @t2(ptr %a, ptr %b) nounwind readonly {37entry:38 %0 = load <2 x i64>, ptr %a, align 16 ; <<2 x i64>> [#uses=1]39 %1 = load <2 x i64>, ptr %b, align 16 ; <<2 x i64>> [#uses=1]40 %2 = sub <2 x i64> %0, %1 ; <<2 x i64>> [#uses=1]41 %3 = bitcast <2 x i64> %2 to <4 x i32> ; <<4 x i32>> [#uses=1]42 ret <4 x i32> %343}44 45; Limited alignment.46; SWIFT: t347; SWIFT: vld1.64 {{.d[0-9]+, d[0-9]+}, \[r[0-9]+}}48; SWIFT: vld1.64 {{.d[0-9]+, d[0-9]+}, \[r[0-9]+}}49; SWIFT: vadd.i64 q50; SWIFT: vst1.64 {{.d[0-9]+, d[0-9]+}, \[r[0-9]+}}51define void @t3(ptr %r, ptr %a, ptr %b) nounwind {52entry:53 %0 = load <2 x i64>, ptr %a, align 854 %1 = load <2 x i64>, ptr %b, align 855 %2 = add <2 x i64> %0, %156 %3 = bitcast <2 x i64> %2 to <4 x i32>57 store <4 x i32> %3, ptr %r, align 858 ret void59}60