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1; RUN: llc < %s -verify-machineinstrs2; RUN: llc < %s -verify-machineinstrs -O03; PR121774;5; This test case spills a QQQQ register.6;7target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:64:128-a0:0:64-n32-S64"8target triple = "armv7-none-linux-gnueabi"9 10%0 = type { ptr, i32, i32, i32, i8 }11%1 = type { ptr }12%2 = type { ptr, ptr, ptr, i32 }13%3 = type { %4 }14%4 = type { ptr, %2, ptr, i8, i8 }15 16declare arm_aapcs_vfpcc void @func1(ptr, ptr nocapture, ptr nocapture, ptr) nounwind17 18declare arm_aapcs_vfpcc ptr @func2()19 20declare arm_aapcs_vfpcc ptr @func3(ptr, ptr, i32)21 22declare arm_aapcs_vfpcc ptr @func4()23 24define arm_aapcs_vfpcc void @foo(ptr nocapture) nounwind align 2 {25 call void @llvm.arm.neon.vst4.p0.v4i32(ptr undef, <4 x i32> <i32 0, i32 1065353216, i32 1073741824, i32 1077936128>, <4 x i32> <i32 1082130432, i32 1084227584, i32 1086324736, i32 1088421888>, <4 x i32> <i32 1090519040, i32 1091567616, i32 1092616192, i32 1093664768>, <4 x i32> <i32 1094713344, i32 1095761920, i32 1096810496, i32 1097859072>, i32 16) nounwind26 %2 = call arm_aapcs_vfpcc ptr @func2() nounwind27 %3 = load ptr, ptr %2, align 428 store float 0.000000e+00, ptr undef, align 429 %4 = call arm_aapcs_vfpcc ptr @func3(ptr undef, ptr undef, i32 2956) nounwind30 call arm_aapcs_vfpcc void @func1(ptr %3, ptr undef, ptr undef, ptr undef)31 %5 = call arm_aapcs_vfpcc ptr @func2() nounwind32 store float 1.000000e+00, ptr undef, align 433 call arm_aapcs_vfpcc void @func1(ptr undef, ptr undef, ptr undef, ptr undef)34 store float 1.500000e+01, ptr undef, align 435 %6 = call arm_aapcs_vfpcc ptr @func4() nounwind36 %7 = call arm_aapcs_vfpcc ptr @func3(ptr undef, ptr undef, i32 2971) nounwind37 %8 = fadd float undef, -1.000000e+0538 store float %8, ptr undef, align 1639 %9 = call arm_aapcs_vfpcc i32 @rand() nounwind40 %10 = fmul float undef, 2.000000e+0541 %11 = fadd float %10, -1.000000e+0542 store float %11, ptr undef, align 443 call void @llvm.arm.neon.vst4.p0.v4i32(ptr undef, <4 x i32> <i32 0, i32 1065353216, i32 1073741824, i32 1077936128>, <4 x i32> <i32 1082130432, i32 1084227584, i32 1086324736, i32 1088421888>, <4 x i32> <i32 1090519040, i32 1091567616, i32 1092616192, i32 1093664768>, <4 x i32> <i32 1094713344, i32 1095761920, i32 1096810496, i32 1097859072>, i32 16) nounwind44 ret void45}46 47declare void @llvm.arm.neon.vst4.p0.v4i32(ptr, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, i32) nounwind48 49declare arm_aapcs_vfpcc i32 @rand()50