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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=armv7a-eabihf -mattr=+neon %s -o - | FileCheck %s3 4;5; SABD6;7 8define <8 x i8> @sabd_8b(<8 x i8> %a, <8 x i8> %b) {9; CHECK-LABEL: sabd_8b:10; CHECK: @ %bb.0:11; CHECK-NEXT: vabd.s8 d0, d0, d112; CHECK-NEXT: bx lr13 %a.sext = sext <8 x i8> %a to <8 x i16>14 %b.sext = sext <8 x i8> %b to <8 x i16>15 %sub = sub <8 x i16> %a.sext, %b.sext16 %abs = call <8 x i16> @llvm.abs.v8i16(<8 x i16> %sub, i1 true)17 %trunc = trunc <8 x i16> %abs to <8 x i8>18 ret <8 x i8> %trunc19}20 21define <16 x i8> @sabd_16b(<16 x i8> %a, <16 x i8> %b) {22; CHECK-LABEL: sabd_16b:23; CHECK: @ %bb.0:24; CHECK-NEXT: vabd.s8 q0, q0, q125; CHECK-NEXT: bx lr26 %a.sext = sext <16 x i8> %a to <16 x i16>27 %b.sext = sext <16 x i8> %b to <16 x i16>28 %sub = sub <16 x i16> %a.sext, %b.sext29 %abs = call <16 x i16> @llvm.abs.v16i16(<16 x i16> %sub, i1 true)30 %trunc = trunc <16 x i16> %abs to <16 x i8>31 ret <16 x i8> %trunc32}33 34define <4 x i16> @sabd_4h(<4 x i16> %a, <4 x i16> %b) {35; CHECK-LABEL: sabd_4h:36; CHECK: @ %bb.0:37; CHECK-NEXT: vabd.s16 d0, d0, d138; CHECK-NEXT: bx lr39 %a.sext = sext <4 x i16> %a to <4 x i32>40 %b.sext = sext <4 x i16> %b to <4 x i32>41 %sub = sub <4 x i32> %a.sext, %b.sext42 %abs = call <4 x i32> @llvm.abs.v4i32(<4 x i32> %sub, i1 true)43 %trunc = trunc <4 x i32> %abs to <4 x i16>44 ret <4 x i16> %trunc45}46 47define <4 x i16> @sabd_4h_promoted_ops(<4 x i8> %a, <4 x i8> %b) {48; CHECK-LABEL: sabd_4h_promoted_ops:49; CHECK: @ %bb.0:50; CHECK-NEXT: vshl.i16 d16, d1, #851; CHECK-NEXT: vshl.i16 d17, d0, #852; CHECK-NEXT: vshr.s16 d16, d16, #853; CHECK-NEXT: vshr.s16 d17, d17, #854; CHECK-NEXT: vabd.s16 d0, d17, d1655; CHECK-NEXT: bx lr56 %a.sext = sext <4 x i8> %a to <4 x i16>57 %b.sext = sext <4 x i8> %b to <4 x i16>58 %sub = sub <4 x i16> %a.sext, %b.sext59 %abs = call <4 x i16> @llvm.abs.v4i16(<4 x i16> %sub, i1 true)60 ret <4 x i16> %abs61}62 63define <8 x i16> @sabd_8h(<8 x i16> %a, <8 x i16> %b) {64; CHECK-LABEL: sabd_8h:65; CHECK: @ %bb.0:66; CHECK-NEXT: vabd.s16 q0, q0, q167; CHECK-NEXT: bx lr68 %a.sext = sext <8 x i16> %a to <8 x i32>69 %b.sext = sext <8 x i16> %b to <8 x i32>70 %sub = sub <8 x i32> %a.sext, %b.sext71 %abs = call <8 x i32> @llvm.abs.v8i32(<8 x i32> %sub, i1 true)72 %trunc = trunc <8 x i32> %abs to <8 x i16>73 ret <8 x i16> %trunc74}75 76define <8 x i16> @sabd_8h_promoted_ops(<8 x i8> %a, <8 x i8> %b) {77; CHECK-LABEL: sabd_8h_promoted_ops:78; CHECK: @ %bb.0:79; CHECK-NEXT: vabdl.s8 q0, d0, d180; CHECK-NEXT: bx lr81 %a.sext = sext <8 x i8> %a to <8 x i16>82 %b.sext = sext <8 x i8> %b to <8 x i16>83 %sub = sub <8 x i16> %a.sext, %b.sext84 %abs = call <8 x i16> @llvm.abs.v8i16(<8 x i16> %sub, i1 true)85 ret <8 x i16> %abs86}87 88define <2 x i32> @sabd_2s(<2 x i32> %a, <2 x i32> %b) {89; CHECK-LABEL: sabd_2s:90; CHECK: @ %bb.0:91; CHECK-NEXT: vabd.s32 d0, d0, d192; CHECK-NEXT: bx lr93 %a.sext = sext <2 x i32> %a to <2 x i64>94 %b.sext = sext <2 x i32> %b to <2 x i64>95 %sub = sub <2 x i64> %a.sext, %b.sext96 %abs = call <2 x i64> @llvm.abs.v2i64(<2 x i64> %sub, i1 true)97 %trunc = trunc <2 x i64> %abs to <2 x i32>98 ret <2 x i32> %trunc99}100 101define <2 x i32> @sabd_2s_promoted_ops(<2 x i16> %a, <2 x i16> %b) {102; CHECK-LABEL: sabd_2s_promoted_ops:103; CHECK: @ %bb.0:104; CHECK-NEXT: vshl.i32 d16, d1, #16105; CHECK-NEXT: vshl.i32 d17, d0, #16106; CHECK-NEXT: vshr.s32 d16, d16, #16107; CHECK-NEXT: vshr.s32 d17, d17, #16108; CHECK-NEXT: vabd.s32 d0, d17, d16109; CHECK-NEXT: bx lr110 %a.sext = sext <2 x i16> %a to <2 x i32>111 %b.sext = sext <2 x i16> %b to <2 x i32>112 %sub = sub <2 x i32> %a.sext, %b.sext113 %abs = call <2 x i32> @llvm.abs.v2i32(<2 x i32> %sub, i1 true)114 ret <2 x i32> %abs115}116 117define <4 x i32> @sabd_4s(<4 x i32> %a, <4 x i32> %b) {118; CHECK-LABEL: sabd_4s:119; CHECK: @ %bb.0:120; CHECK-NEXT: vabd.s32 q0, q0, q1121; CHECK-NEXT: bx lr122 %a.sext = sext <4 x i32> %a to <4 x i64>123 %b.sext = sext <4 x i32> %b to <4 x i64>124 %sub = sub <4 x i64> %a.sext, %b.sext125 %abs = call <4 x i64> @llvm.abs.v4i64(<4 x i64> %sub, i1 true)126 %trunc = trunc <4 x i64> %abs to <4 x i32>127 ret <4 x i32> %trunc128}129 130define <4 x i32> @sabd_4s_promoted_ops(<4 x i16> %a, <4 x i16> %b) {131; CHECK-LABEL: sabd_4s_promoted_ops:132; CHECK: @ %bb.0:133; CHECK-NEXT: vabdl.s16 q0, d0, d1134; CHECK-NEXT: bx lr135 %a.sext = sext <4 x i16> %a to <4 x i32>136 %b.sext = sext <4 x i16> %b to <4 x i32>137 %sub = sub <4 x i32> %a.sext, %b.sext138 %abs = call <4 x i32> @llvm.abs.v4i32(<4 x i32> %sub, i1 true)139 ret <4 x i32> %abs140}141 142define <2 x i64> @sabd_2d(<2 x i64> %a, <2 x i64> %b) {143; CHECK-LABEL: sabd_2d:144; CHECK: @ %bb.0:145; CHECK-NEXT: .save {r4, r5, r6, lr}146; CHECK-NEXT: push {r4, r5, r6, lr}147; CHECK-NEXT: vmov r0, r1, d1148; CHECK-NEXT: mov r6, #0149; CHECK-NEXT: vmov r2, r3, d3150; CHECK-NEXT: vmov r12, lr, d0151; CHECK-NEXT: vmov r4, r5, d2152; CHECK-NEXT: vsub.i64 q8, q0, q1153; CHECK-NEXT: subs r0, r2, r0154; CHECK-NEXT: sbcs r0, r3, r1155; CHECK-NEXT: mov r0, #0156; CHECK-NEXT: movwlt r0, #1157; CHECK-NEXT: cmp r0, #0158; CHECK-NEXT: mvnne r0, #0159; CHECK-NEXT: subs r1, r4, r12160; CHECK-NEXT: sbcs r1, r5, lr161; CHECK-NEXT: vdup.32 d19, r0162; CHECK-NEXT: movwlt r6, #1163; CHECK-NEXT: cmp r6, #0164; CHECK-NEXT: mvnne r6, #0165; CHECK-NEXT: vdup.32 d18, r6166; CHECK-NEXT: veor q8, q8, q9167; CHECK-NEXT: vsub.i64 q0, q9, q8168; CHECK-NEXT: pop {r4, r5, r6, pc}169 %a.sext = sext <2 x i64> %a to <2 x i128>170 %b.sext = sext <2 x i64> %b to <2 x i128>171 %sub = sub <2 x i128> %a.sext, %b.sext172 %abs = call <2 x i128> @llvm.abs.v2i128(<2 x i128> %sub, i1 true)173 %trunc = trunc <2 x i128> %abs to <2 x i64>174 ret <2 x i64> %trunc175}176 177define <2 x i64> @sabd_2d_promoted_ops(<2 x i32> %a, <2 x i32> %b) {178; CHECK-LABEL: sabd_2d_promoted_ops:179; CHECK: @ %bb.0:180; CHECK-NEXT: vabdl.s32 q0, d0, d1181; CHECK-NEXT: bx lr182 %a.sext = sext <2 x i32> %a to <2 x i64>183 %b.sext = sext <2 x i32> %b to <2 x i64>184 %sub = sub <2 x i64> %a.sext, %b.sext185 %abs = call <2 x i64> @llvm.abs.v2i64(<2 x i64> %sub, i1 true)186 ret <2 x i64> %abs187}188 189;190; UABD191;192 193define <8 x i8> @uabd_8b(<8 x i8> %a, <8 x i8> %b) {194; CHECK-LABEL: uabd_8b:195; CHECK: @ %bb.0:196; CHECK-NEXT: vabd.u8 d0, d0, d1197; CHECK-NEXT: bx lr198 %a.zext = zext <8 x i8> %a to <8 x i16>199 %b.zext = zext <8 x i8> %b to <8 x i16>200 %sub = sub <8 x i16> %a.zext, %b.zext201 %abs = call <8 x i16> @llvm.abs.v8i16(<8 x i16> %sub, i1 true)202 %trunc = trunc <8 x i16> %abs to <8 x i8>203 ret <8 x i8> %trunc204}205 206define <16 x i8> @uabd_16b(<16 x i8> %a, <16 x i8> %b) {207; CHECK-LABEL: uabd_16b:208; CHECK: @ %bb.0:209; CHECK-NEXT: vabd.u8 q0, q0, q1210; CHECK-NEXT: bx lr211 %a.zext = zext <16 x i8> %a to <16 x i16>212 %b.zext = zext <16 x i8> %b to <16 x i16>213 %sub = sub <16 x i16> %a.zext, %b.zext214 %abs = call <16 x i16> @llvm.abs.v16i16(<16 x i16> %sub, i1 true)215 %trunc = trunc <16 x i16> %abs to <16 x i8>216 ret <16 x i8> %trunc217}218 219define <4 x i16> @uabd_4h(<4 x i16> %a, <4 x i16> %b) {220; CHECK-LABEL: uabd_4h:221; CHECK: @ %bb.0:222; CHECK-NEXT: vabd.u16 d0, d0, d1223; CHECK-NEXT: bx lr224 %a.zext = zext <4 x i16> %a to <4 x i32>225 %b.zext = zext <4 x i16> %b to <4 x i32>226 %sub = sub <4 x i32> %a.zext, %b.zext227 %abs = call <4 x i32> @llvm.abs.v4i32(<4 x i32> %sub, i1 true)228 %trunc = trunc <4 x i32> %abs to <4 x i16>229 ret <4 x i16> %trunc230}231 232define <4 x i16> @uabd_4h_promoted_ops(<4 x i8> %a, <4 x i8> %b) {233; CHECK-LABEL: uabd_4h_promoted_ops:234; CHECK: @ %bb.0:235; CHECK-NEXT: vbic.i16 d1, #0xff00236; CHECK-NEXT: vbic.i16 d0, #0xff00237; CHECK-NEXT: vabd.u16 d0, d0, d1238; CHECK-NEXT: bx lr239 %a.zext = zext <4 x i8> %a to <4 x i16>240 %b.zext = zext <4 x i8> %b to <4 x i16>241 %sub = sub <4 x i16> %a.zext, %b.zext242 %abs = call <4 x i16> @llvm.abs.v4i16(<4 x i16> %sub, i1 true)243 ret <4 x i16> %abs244}245 246define <8 x i16> @uabd_8h(<8 x i16> %a, <8 x i16> %b) {247; CHECK-LABEL: uabd_8h:248; CHECK: @ %bb.0:249; CHECK-NEXT: vabd.u16 q0, q0, q1250; CHECK-NEXT: bx lr251 %a.zext = zext <8 x i16> %a to <8 x i32>252 %b.zext = zext <8 x i16> %b to <8 x i32>253 %sub = sub <8 x i32> %a.zext, %b.zext254 %abs = call <8 x i32> @llvm.abs.v8i32(<8 x i32> %sub, i1 true)255 %trunc = trunc <8 x i32> %abs to <8 x i16>256 ret <8 x i16> %trunc257}258 259define <8 x i16> @uabd_8h_promoted_ops(<8 x i8> %a, <8 x i8> %b) {260; CHECK-LABEL: uabd_8h_promoted_ops:261; CHECK: @ %bb.0:262; CHECK-NEXT: vabdl.u8 q0, d0, d1263; CHECK-NEXT: bx lr264 %a.zext = zext <8 x i8> %a to <8 x i16>265 %b.zext = zext <8 x i8> %b to <8 x i16>266 %sub = sub <8 x i16> %a.zext, %b.zext267 %abs = call <8 x i16> @llvm.abs.v8i16(<8 x i16> %sub, i1 true)268 ret <8 x i16> %abs269}270 271define <2 x i32> @uabd_2s(<2 x i32> %a, <2 x i32> %b) {272; CHECK-LABEL: uabd_2s:273; CHECK: @ %bb.0:274; CHECK-NEXT: vabd.u32 d0, d0, d1275; CHECK-NEXT: bx lr276 %a.zext = zext <2 x i32> %a to <2 x i64>277 %b.zext = zext <2 x i32> %b to <2 x i64>278 %sub = sub <2 x i64> %a.zext, %b.zext279 %abs = call <2 x i64> @llvm.abs.v2i64(<2 x i64> %sub, i1 true)280 %trunc = trunc <2 x i64> %abs to <2 x i32>281 ret <2 x i32> %trunc282}283 284define <2 x i32> @uabd_2s_promoted_ops(<2 x i16> %a, <2 x i16> %b) {285; CHECK-LABEL: uabd_2s_promoted_ops:286; CHECK: @ %bb.0:287; CHECK-NEXT: vmov.i32 d16, #0xffff288; CHECK-NEXT: vand d17, d1, d16289; CHECK-NEXT: vand d16, d0, d16290; CHECK-NEXT: vabd.u32 d0, d16, d17291; CHECK-NEXT: bx lr292 %a.zext = zext <2 x i16> %a to <2 x i32>293 %b.zext = zext <2 x i16> %b to <2 x i32>294 %sub = sub <2 x i32> %a.zext, %b.zext295 %abs = call <2 x i32> @llvm.abs.v2i32(<2 x i32> %sub, i1 true)296 ret <2 x i32> %abs297}298 299define <4 x i32> @uabd_4s(<4 x i32> %a, <4 x i32> %b) {300; CHECK-LABEL: uabd_4s:301; CHECK: @ %bb.0:302; CHECK-NEXT: vabd.u32 q0, q0, q1303; CHECK-NEXT: bx lr304 %a.zext = zext <4 x i32> %a to <4 x i64>305 %b.zext = zext <4 x i32> %b to <4 x i64>306 %sub = sub <4 x i64> %a.zext, %b.zext307 %abs = call <4 x i64> @llvm.abs.v4i64(<4 x i64> %sub, i1 true)308 %trunc = trunc <4 x i64> %abs to <4 x i32>309 ret <4 x i32> %trunc310}311 312define <4 x i32> @uabd_4s_promoted_ops(<4 x i16> %a, <4 x i16> %b) {313; CHECK-LABEL: uabd_4s_promoted_ops:314; CHECK: @ %bb.0:315; CHECK-NEXT: vabdl.u16 q0, d0, d1316; CHECK-NEXT: bx lr317 %a.zext = zext <4 x i16> %a to <4 x i32>318 %b.zext = zext <4 x i16> %b to <4 x i32>319 %sub = sub <4 x i32> %a.zext, %b.zext320 %abs = call <4 x i32> @llvm.abs.v4i32(<4 x i32> %sub, i1 true)321 ret <4 x i32> %abs322}323 324define <2 x i64> @uabd_2d(<2 x i64> %a, <2 x i64> %b) {325; CHECK-LABEL: uabd_2d:326; CHECK: @ %bb.0:327; CHECK-NEXT: vqsub.u64 q8, q1, q0328; CHECK-NEXT: vqsub.u64 q9, q0, q1329; CHECK-NEXT: vorr q0, q9, q8330; CHECK-NEXT: bx lr331 %a.zext = zext <2 x i64> %a to <2 x i128>332 %b.zext = zext <2 x i64> %b to <2 x i128>333 %sub = sub <2 x i128> %a.zext, %b.zext334 %abs = call <2 x i128> @llvm.abs.v2i128(<2 x i128> %sub, i1 true)335 %trunc = trunc <2 x i128> %abs to <2 x i64>336 ret <2 x i64> %trunc337}338 339define <2 x i64> @uabd_2d_promoted_ops(<2 x i32> %a, <2 x i32> %b) {340; CHECK-LABEL: uabd_2d_promoted_ops:341; CHECK: @ %bb.0:342; CHECK-NEXT: vabdl.u32 q0, d0, d1343; CHECK-NEXT: bx lr344 %a.zext = zext <2 x i32> %a to <2 x i64>345 %b.zext = zext <2 x i32> %b to <2 x i64>346 %sub = sub <2 x i64> %a.zext, %b.zext347 %abs = call <2 x i64> @llvm.abs.v2i64(<2 x i64> %sub, i1 true)348 ret <2 x i64> %abs349}350 351define <16 x i8> @uabd_v16i8_nuw(<16 x i8> %a, <16 x i8> %b) {352; CHECK-LABEL: uabd_v16i8_nuw:353; CHECK: @ %bb.0:354; CHECK-NEXT: vsub.i8 q8, q0, q1355; CHECK-NEXT: vabs.s8 q0, q8356; CHECK-NEXT: bx lr357 %sub = sub nuw <16 x i8> %a, %b358 %abs = call <16 x i8> @llvm.abs.v16i8(<16 x i8> %sub, i1 true)359 ret <16 x i8> %abs360}361 362define <8 x i16> @uabd_v8i16_nuw(<8 x i16> %a, <8 x i16> %b) {363; CHECK-LABEL: uabd_v8i16_nuw:364; CHECK: @ %bb.0:365; CHECK-NEXT: vsub.i16 q8, q0, q1366; CHECK-NEXT: vabs.s16 q0, q8367; CHECK-NEXT: bx lr368 %sub = sub nuw <8 x i16> %a, %b369 %abs = call <8 x i16> @llvm.abs.v8i16(<8 x i16> %sub, i1 true)370 ret <8 x i16> %abs371}372 373define <4 x i32> @uabd_v4i32_nuw(<4 x i32> %a, <4 x i32> %b) {374; CHECK-LABEL: uabd_v4i32_nuw:375; CHECK: @ %bb.0:376; CHECK-NEXT: vsub.i32 q8, q0, q1377; CHECK-NEXT: vabs.s32 q0, q8378; CHECK-NEXT: bx lr379 %sub = sub nuw <4 x i32> %a, %b380 %abs = call <4 x i32> @llvm.abs.v4i32(<4 x i32> %sub, i1 true)381 ret <4 x i32> %abs382}383 384define <2 x i64> @uabd_v2i64_nuw(<2 x i64> %a, <2 x i64> %b) {385; CHECK-LABEL: uabd_v2i64_nuw:386; CHECK: @ %bb.0:387; CHECK-NEXT: vsub.i64 q8, q0, q1388; CHECK-NEXT: vshr.s64 q9, q8, #63389; CHECK-NEXT: veor q8, q8, q9390; CHECK-NEXT: vsub.i64 q0, q8, q9391; CHECK-NEXT: bx lr392 %sub = sub nuw <2 x i64> %a, %b393 %abs = call <2 x i64> @llvm.abs.v2i64(<2 x i64> %sub, i1 true)394 ret <2 x i64> %abs395}396 397define <16 x i8> @sabd_v16i8_nsw(<16 x i8> %a, <16 x i8> %b) {398; CHECK-LABEL: sabd_v16i8_nsw:399; CHECK: @ %bb.0:400; CHECK-NEXT: vabd.s8 q0, q0, q1401; CHECK-NEXT: bx lr402 %sub = sub nsw <16 x i8> %a, %b403 %abs = call <16 x i8> @llvm.abs.v16i8(<16 x i8> %sub, i1 true)404 ret <16 x i8> %abs405}406 407define <8 x i16> @sabd_v8i16_nsw(<8 x i16> %a, <8 x i16> %b) {408; CHECK-LABEL: sabd_v8i16_nsw:409; CHECK: @ %bb.0:410; CHECK-NEXT: vabd.s16 q0, q0, q1411; CHECK-NEXT: bx lr412 %sub = sub nsw <8 x i16> %a, %b413 %abs = call <8 x i16> @llvm.abs.v8i16(<8 x i16> %sub, i1 true)414 ret <8 x i16> %abs415}416 417define <4 x i32> @sabd_v4i32_nsw(<4 x i32> %a, <4 x i32> %b) {418; CHECK-LABEL: sabd_v4i32_nsw:419; CHECK: @ %bb.0:420; CHECK-NEXT: vabd.s32 q0, q0, q1421; CHECK-NEXT: bx lr422 %sub = sub nsw <4 x i32> %a, %b423 %abs = call <4 x i32> @llvm.abs.v4i32(<4 x i32> %sub, i1 true)424 ret <4 x i32> %abs425}426 427define <2 x i64> @sabd_v2i64_nsw(<2 x i64> %a, <2 x i64> %b) {428; CHECK-LABEL: sabd_v2i64_nsw:429; CHECK: @ %bb.0:430; CHECK-NEXT: vsub.i64 q8, q0, q1431; CHECK-NEXT: vshr.s64 q9, q8, #63432; CHECK-NEXT: veor q8, q8, q9433; CHECK-NEXT: vsub.i64 q0, q8, q9434; CHECK-NEXT: bx lr435 %sub = sub nsw <2 x i64> %a, %b436 %abs = call <2 x i64> @llvm.abs.v2i64(<2 x i64> %sub, i1 true)437 ret <2 x i64> %abs438}439 440define <16 x i8> @smaxmin_v16i8(<16 x i8> %0, <16 x i8> %1) {441; CHECK-LABEL: smaxmin_v16i8:442; CHECK: @ %bb.0:443; CHECK-NEXT: vabd.s8 q0, q0, q1444; CHECK-NEXT: bx lr445 %a = tail call <16 x i8> @llvm.smax.v16i8(<16 x i8> %0, <16 x i8> %1)446 %b = tail call <16 x i8> @llvm.smin.v16i8(<16 x i8> %0, <16 x i8> %1)447 %sub = sub <16 x i8> %a, %b448 ret <16 x i8> %sub449}450 451define <8 x i16> @smaxmin_v8i16(<8 x i16> %0, <8 x i16> %1) {452; CHECK-LABEL: smaxmin_v8i16:453; CHECK: @ %bb.0:454; CHECK-NEXT: vabd.s16 q0, q0, q1455; CHECK-NEXT: bx lr456 %a = tail call <8 x i16> @llvm.smax.v8i16(<8 x i16> %0, <8 x i16> %1)457 %b = tail call <8 x i16> @llvm.smin.v8i16(<8 x i16> %0, <8 x i16> %1)458 %sub = sub <8 x i16> %a, %b459 ret <8 x i16> %sub460}461 462define <4 x i32> @smaxmin_v4i32(<4 x i32> %0, <4 x i32> %1) {463; CHECK-LABEL: smaxmin_v4i32:464; CHECK: @ %bb.0:465; CHECK-NEXT: vabd.s32 q0, q0, q1466; CHECK-NEXT: bx lr467 %a = tail call <4 x i32> @llvm.smax.v4i32(<4 x i32> %0, <4 x i32> %1)468 %b = tail call <4 x i32> @llvm.smin.v4i32(<4 x i32> %0, <4 x i32> %1)469 %sub = sub <4 x i32> %a, %b470 ret <4 x i32> %sub471}472 473define <2 x i64> @smaxmin_v2i64(<2 x i64> %0, <2 x i64> %1) {474; CHECK-LABEL: smaxmin_v2i64:475; CHECK: @ %bb.0:476; CHECK-NEXT: .save {r4, r5, r6, lr}477; CHECK-NEXT: push {r4, r5, r6, lr}478; CHECK-NEXT: vmov r0, r1, d1479; CHECK-NEXT: mov r6, #0480; CHECK-NEXT: vmov r2, r3, d3481; CHECK-NEXT: vmov r12, lr, d0482; CHECK-NEXT: vmov r4, r5, d2483; CHECK-NEXT: vsub.i64 q8, q0, q1484; CHECK-NEXT: subs r0, r2, r0485; CHECK-NEXT: sbcs r0, r3, r1486; CHECK-NEXT: mov r0, #0487; CHECK-NEXT: movwlt r0, #1488; CHECK-NEXT: cmp r0, #0489; CHECK-NEXT: mvnne r0, #0490; CHECK-NEXT: subs r1, r4, r12491; CHECK-NEXT: sbcs r1, r5, lr492; CHECK-NEXT: vdup.32 d19, r0493; CHECK-NEXT: movwlt r6, #1494; CHECK-NEXT: cmp r6, #0495; CHECK-NEXT: mvnne r6, #0496; CHECK-NEXT: vdup.32 d18, r6497; CHECK-NEXT: veor q8, q8, q9498; CHECK-NEXT: vsub.i64 q0, q9, q8499; CHECK-NEXT: pop {r4, r5, r6, pc}500 %a = tail call <2 x i64> @llvm.smax.v2i64(<2 x i64> %0, <2 x i64> %1)501 %b = tail call <2 x i64> @llvm.smin.v2i64(<2 x i64> %0, <2 x i64> %1)502 %sub = sub <2 x i64> %a, %b503 ret <2 x i64> %sub504}505 506define <16 x i8> @umaxmin_v16i8(<16 x i8> %0, <16 x i8> %1) {507; CHECK-LABEL: umaxmin_v16i8:508; CHECK: @ %bb.0:509; CHECK-NEXT: vabd.u8 q0, q0, q1510; CHECK-NEXT: bx lr511 %a = tail call <16 x i8> @llvm.umax.v16i8(<16 x i8> %0, <16 x i8> %1)512 %b = tail call <16 x i8> @llvm.umin.v16i8(<16 x i8> %0, <16 x i8> %1)513 %sub = sub <16 x i8> %a, %b514 ret <16 x i8> %sub515}516 517define <8 x i16> @umaxmin_v8i16(<8 x i16> %0, <8 x i16> %1) {518; CHECK-LABEL: umaxmin_v8i16:519; CHECK: @ %bb.0:520; CHECK-NEXT: vabd.u16 q0, q0, q1521; CHECK-NEXT: bx lr522 %a = tail call <8 x i16> @llvm.umax.v8i16(<8 x i16> %0, <8 x i16> %1)523 %b = tail call <8 x i16> @llvm.umin.v8i16(<8 x i16> %0, <8 x i16> %1)524 %sub = sub <8 x i16> %a, %b525 ret <8 x i16> %sub526}527 528define <4 x i32> @umaxmin_v4i32(<4 x i32> %0, <4 x i32> %1) {529; CHECK-LABEL: umaxmin_v4i32:530; CHECK: @ %bb.0:531; CHECK-NEXT: vabd.u32 q0, q0, q1532; CHECK-NEXT: bx lr533 %a = tail call <4 x i32> @llvm.umax.v4i32(<4 x i32> %0, <4 x i32> %1)534 %b = tail call <4 x i32> @llvm.umin.v4i32(<4 x i32> %0, <4 x i32> %1)535 %sub = sub <4 x i32> %a, %b536 ret <4 x i32> %sub537}538 539define <2 x i64> @umaxmin_v2i64(<2 x i64> %0, <2 x i64> %1) {540; CHECK-LABEL: umaxmin_v2i64:541; CHECK: @ %bb.0:542; CHECK-NEXT: vqsub.u64 q8, q1, q0543; CHECK-NEXT: vqsub.u64 q9, q0, q1544; CHECK-NEXT: vorr q0, q9, q8545; CHECK-NEXT: bx lr546 %a = tail call <2 x i64> @llvm.umax.v2i64(<2 x i64> %0, <2 x i64> %1)547 %b = tail call <2 x i64> @llvm.umin.v2i64(<2 x i64> %0, <2 x i64> %1)548 %sub = sub <2 x i64> %a, %b549 ret <2 x i64> %sub550}551 552define <16 x i8> @umaxmin_v16i8_com1(<16 x i8> %0, <16 x i8> %1) {553; CHECK-LABEL: umaxmin_v16i8_com1:554; CHECK: @ %bb.0:555; CHECK-NEXT: vabd.u8 q0, q0, q1556; CHECK-NEXT: bx lr557 %a = tail call <16 x i8> @llvm.umax.v16i8(<16 x i8> %0, <16 x i8> %1)558 %b = tail call <16 x i8> @llvm.umin.v16i8(<16 x i8> %1, <16 x i8> %0)559 %sub = sub <16 x i8> %a, %b560 ret <16 x i8> %sub561}562