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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s3 4define <4 x i32> @test1(<4 x i32> %a) nounwind {5; CHECK-LABEL: test1:6; CHECK: @ %bb.0:7; CHECK-NEXT: vmov d17, r2, r38; CHECK-NEXT: vmov d16, r0, r19; CHECK-NEXT: vabs.s32 q8, q810; CHECK-NEXT: vmov r0, r1, d1611; CHECK-NEXT: vmov r2, r3, d1712; CHECK-NEXT: mov pc, lr13 %tmp1neg = sub <4 x i32> zeroinitializer, %a14 %b = icmp sgt <4 x i32> %a, <i32 -1, i32 -1, i32 -1, i32 -1>15 %abs = select <4 x i1> %b, <4 x i32> %a, <4 x i32> %tmp1neg16 ret <4 x i32> %abs17}18 19define <4 x i32> @test2(<4 x i32> %a) nounwind {20; CHECK-LABEL: test2:21; CHECK: @ %bb.0:22; CHECK-NEXT: vmov d17, r2, r323; CHECK-NEXT: vmov d16, r0, r124; CHECK-NEXT: vabs.s32 q8, q825; CHECK-NEXT: vmov r0, r1, d1626; CHECK-NEXT: vmov r2, r3, d1727; CHECK-NEXT: mov pc, lr28 %tmp1neg = sub <4 x i32> zeroinitializer, %a29 %b = icmp sge <4 x i32> %a, zeroinitializer30 %abs = select <4 x i1> %b, <4 x i32> %a, <4 x i32> %tmp1neg31 ret <4 x i32> %abs32}33 34define <8 x i16> @test3(<8 x i16> %a) nounwind {35; CHECK-LABEL: test3:36; CHECK: @ %bb.0:37; CHECK-NEXT: vmov d17, r2, r338; CHECK-NEXT: vmov d16, r0, r139; CHECK-NEXT: vabs.s16 q8, q840; CHECK-NEXT: vmov r0, r1, d1641; CHECK-NEXT: vmov r2, r3, d1742; CHECK-NEXT: mov pc, lr43 %tmp1neg = sub <8 x i16> zeroinitializer, %a44 %b = icmp sgt <8 x i16> %a, zeroinitializer45 %abs = select <8 x i1> %b, <8 x i16> %a, <8 x i16> %tmp1neg46 ret <8 x i16> %abs47}48 49define <16 x i8> @test4(<16 x i8> %a) nounwind {50; CHECK-LABEL: test4:51; CHECK: @ %bb.0:52; CHECK-NEXT: vmov d17, r2, r353; CHECK-NEXT: vmov d16, r0, r154; CHECK-NEXT: vabs.s8 q8, q855; CHECK-NEXT: vmov r0, r1, d1656; CHECK-NEXT: vmov r2, r3, d1757; CHECK-NEXT: mov pc, lr58 %tmp1neg = sub <16 x i8> zeroinitializer, %a59 %b = icmp slt <16 x i8> %a, zeroinitializer60 %abs = select <16 x i1> %b, <16 x i8> %tmp1neg, <16 x i8> %a61 ret <16 x i8> %abs62}63 64define <4 x i32> @test5(<4 x i32> %a) nounwind {65; CHECK-LABEL: test5:66; CHECK: @ %bb.0:67; CHECK-NEXT: vmov d17, r2, r368; CHECK-NEXT: vmov d16, r0, r169; CHECK-NEXT: vabs.s32 q8, q870; CHECK-NEXT: vmov r0, r1, d1671; CHECK-NEXT: vmov r2, r3, d1772; CHECK-NEXT: mov pc, lr73 %tmp1neg = sub <4 x i32> zeroinitializer, %a74 %b = icmp sle <4 x i32> %a, zeroinitializer75 %abs = select <4 x i1> %b, <4 x i32> %tmp1neg, <4 x i32> %a76 ret <4 x i32> %abs77}78 79define <2 x i32> @test6(<2 x i32> %a) nounwind {80; CHECK-LABEL: test6:81; CHECK: @ %bb.0:82; CHECK-NEXT: vmov d16, r0, r183; CHECK-NEXT: vabs.s32 d16, d1684; CHECK-NEXT: vmov r0, r1, d1685; CHECK-NEXT: mov pc, lr86 %tmp1neg = sub <2 x i32> zeroinitializer, %a87 %b = icmp sgt <2 x i32> %a, <i32 -1, i32 -1>88 %abs = select <2 x i1> %b, <2 x i32> %a, <2 x i32> %tmp1neg89 ret <2 x i32> %abs90}91 92define <2 x i32> @test7(<2 x i32> %a) nounwind {93; CHECK-LABEL: test7:94; CHECK: @ %bb.0:95; CHECK-NEXT: vmov d16, r0, r196; CHECK-NEXT: vabs.s32 d16, d1697; CHECK-NEXT: vmov r0, r1, d1698; CHECK-NEXT: mov pc, lr99 %tmp1neg = sub <2 x i32> zeroinitializer, %a100 %b = icmp sge <2 x i32> %a, zeroinitializer101 %abs = select <2 x i1> %b, <2 x i32> %a, <2 x i32> %tmp1neg102 ret <2 x i32> %abs103}104 105define <4 x i16> @test8(<4 x i16> %a) nounwind {106; CHECK-LABEL: test8:107; CHECK: @ %bb.0:108; CHECK-NEXT: vmov d16, r0, r1109; CHECK-NEXT: vabs.s16 d16, d16110; CHECK-NEXT: vmov r0, r1, d16111; CHECK-NEXT: mov pc, lr112 %tmp1neg = sub <4 x i16> zeroinitializer, %a113 %b = icmp sgt <4 x i16> %a, zeroinitializer114 %abs = select <4 x i1> %b, <4 x i16> %a, <4 x i16> %tmp1neg115 ret <4 x i16> %abs116}117 118define <8 x i8> @test9(<8 x i8> %a) nounwind {119; CHECK-LABEL: test9:120; CHECK: @ %bb.0:121; CHECK-NEXT: vmov d16, r0, r1122; CHECK-NEXT: vabs.s8 d16, d16123; CHECK-NEXT: vmov r0, r1, d16124; CHECK-NEXT: mov pc, lr125 %tmp1neg = sub <8 x i8> zeroinitializer, %a126 %b = icmp slt <8 x i8> %a, zeroinitializer127 %abs = select <8 x i1> %b, <8 x i8> %tmp1neg, <8 x i8> %a128 ret <8 x i8> %abs129}130 131define <2 x i32> @test10(<2 x i32> %a) nounwind {132; CHECK-LABEL: test10:133; CHECK: @ %bb.0:134; CHECK-NEXT: vmov d16, r0, r1135; CHECK-NEXT: vabs.s32 d16, d16136; CHECK-NEXT: vmov r0, r1, d16137; CHECK-NEXT: mov pc, lr138 %tmp1neg = sub <2 x i32> zeroinitializer, %a139 %b = icmp sle <2 x i32> %a, zeroinitializer140 %abs = select <2 x i1> %b, <2 x i32> %tmp1neg, <2 x i32> %a141 ret <2 x i32> %abs142}143 144;; Check that absdiff patterns as emitted by log2 shuffles are145;; matched by VABD.146 147define <4 x i32> @test11(<4 x i16> %a, <4 x i16> %b) nounwind {148; CHECK-LABEL: test11:149; CHECK: @ %bb.0:150; CHECK-NEXT: vmov d16, r2, r3151; CHECK-NEXT: vmov d17, r0, r1152; CHECK-NEXT: vabdl.u16 q8, d17, d16153; CHECK-NEXT: vmov r0, r1, d16154; CHECK-NEXT: vmov r2, r3, d17155; CHECK-NEXT: mov pc, lr156 %zext1 = zext <4 x i16> %a to <4 x i32>157 %zext2 = zext <4 x i16> %b to <4 x i32>158 %diff = sub <4 x i32> %zext1, %zext2159 %shift1 = ashr <4 x i32> %diff, <i32 31, i32 31, i32 31, i32 31>160 %add1 = add <4 x i32> %shift1, %diff161 %res = xor <4 x i32> %shift1, %add1162 ret <4 x i32> %res163}164define <8 x i16> @test12(<8 x i8> %a, <8 x i8> %b) nounwind {165; CHECK-LABEL: test12:166; CHECK: @ %bb.0:167; CHECK-NEXT: vmov d16, r2, r3168; CHECK-NEXT: vmov d17, r0, r1169; CHECK-NEXT: vabdl.u8 q8, d17, d16170; CHECK-NEXT: vmov r0, r1, d16171; CHECK-NEXT: vmov r2, r3, d17172; CHECK-NEXT: mov pc, lr173 %zext1 = zext <8 x i8> %a to <8 x i16>174 %zext2 = zext <8 x i8> %b to <8 x i16>175 %diff = sub <8 x i16> %zext1, %zext2176 %shift1 = ashr <8 x i16> %diff,<i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>177 %add1 = add <8 x i16> %shift1, %diff178 %res = xor <8 x i16> %shift1, %add1179 ret <8 x i16> %res180}181 182define <2 x i64> @test13(<2 x i32> %a, <2 x i32> %b) nounwind {183; CHECK-LABEL: test13:184; CHECK: @ %bb.0:185; CHECK-NEXT: vmov d16, r2, r3186; CHECK-NEXT: vmov d17, r0, r1187; CHECK-NEXT: vabdl.u32 q8, d17, d16188; CHECK-NEXT: vmov r0, r1, d16189; CHECK-NEXT: vmov r2, r3, d17190; CHECK-NEXT: mov pc, lr191 %zext1 = zext <2 x i32> %a to <2 x i64>192 %zext2 = zext <2 x i32> %b to <2 x i64>193 %diff = sub <2 x i64> %zext1, %zext2194 %shift1 = ashr <2 x i64> %diff,<i64 63, i64 63>195 %add1 = add <2 x i64> %shift1, %diff196 %res = xor <2 x i64> %shift1, %add1197 ret <2 x i64> %res198}199