118 lines · plain
1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -o - %s -mtriple=armv7-- -verify-machineinstrs -run-pass=peephole-opt | FileCheck %s3#4# Make sure we do not crash on this input.5# Note that this input could in principle be optimized, but right now we don't6# have this case implemented so the output should simply be unchanged.7 8---9name: func010tracksRegLiveness: true11body: |12 ; CHECK-LABEL: name: func013 ; CHECK: bb.0:14 ; CHECK: successors: %bb.2(0x40000000), %bb.1(0x40000000)15 ; CHECK: Bcc %bb.2, 1 /* CC::ne */, undef $cpsr16 ; CHECK: bb.1:17 ; CHECK: successors: %bb.3(0x80000000)18 ; CHECK: [[DEF:%[0-9]+]]:dpr = IMPLICIT_DEF19 ; CHECK: [[VMOVRRD:%[0-9]+]]:gpr, [[VMOVRRD1:%[0-9]+]]:gpr = VMOVRRD [[DEF]], 14 /* CC::al */, $noreg20 ; CHECK: B %bb.321 ; CHECK: bb.2:22 ; CHECK: successors: %bb.3(0x80000000)23 ; CHECK: [[DEF1:%[0-9]+]]:spr = IMPLICIT_DEF24 ; CHECK: [[VMOVRS:%[0-9]+]]:gpr = VMOVRS [[DEF1]], 14 /* CC::al */, $noreg25 ; CHECK: bb.3:26 ; CHECK: [[PHI:%[0-9]+]]:gpr = PHI [[VMOVRRD]], %bb.1, [[VMOVRS]], %bb.227 ; CHECK: [[VMOVSR:%[0-9]+]]:spr = VMOVSR [[PHI]], 14 /* CC::al */, $noreg28 bb.0:29 Bcc %bb.2, 1, undef $cpsr30 31 bb.1:32 %0:dpr = IMPLICIT_DEF33 %1:gpr, %2:gpr = VMOVRRD %0:dpr, 14, $noreg34 B %bb.335 36 bb.2:37 %3:spr = IMPLICIT_DEF38 %4:gpr = VMOVRS %3:spr, 14, $noreg39 40 bb.3:41 %5:gpr = PHI %1, %bb.1, %4, %bb.242 %6:spr = VMOVSR %5, 14, $noreg43...44 45---46name: func147tracksRegLiveness: true48body: |49 ; CHECK-LABEL: name: func150 ; CHECK: bb.0:51 ; CHECK: successors: %bb.2(0x40000000), %bb.1(0x40000000)52 ; CHECK: Bcc %bb.2, 1 /* CC::ne */, undef $cpsr53 ; CHECK: bb.1:54 ; CHECK: successors: %bb.3(0x80000000)55 ; CHECK: [[DEF:%[0-9]+]]:spr = IMPLICIT_DEF56 ; CHECK: [[VMOVRS:%[0-9]+]]:gpr = VMOVRS [[DEF]], 14 /* CC::al */, $noreg57 ; CHECK: B %bb.358 ; CHECK: bb.2:59 ; CHECK: successors: %bb.3(0x80000000)60 ; CHECK: [[DEF1:%[0-9]+]]:spr = IMPLICIT_DEF61 ; CHECK: [[VMOVRS1:%[0-9]+]]:gpr = VMOVRS [[DEF1]], 14 /* CC::al */, $noreg62 ; CHECK: bb.3:63 ; CHECK: [[PHI:%[0-9]+]]:spr = PHI [[DEF]], %bb.1, [[DEF1]], %bb.264 ; CHECK: [[PHI1:%[0-9]+]]:gpr = PHI [[VMOVRS]], %bb.1, [[VMOVRS1]], %bb.265 ; CHECK: [[COPY:%[0-9]+]]:spr = COPY [[PHI]]66 bb.0:67 Bcc %bb.2, 1, undef $cpsr68 69 bb.1:70 %1:spr = IMPLICIT_DEF71 %0:gpr = VMOVRS %1, 14, $noreg72 B %bb.373 74 bb.2:75 %3:spr = IMPLICIT_DEF76 %2:gpr = VMOVRS %3:spr, 14, $noreg77 78 bb.3:79 %4:gpr = PHI %0, %bb.1, %2, %bb.280 %5:spr = VMOVSR %4, 14, $noreg81...82 83# The current implementation doesn't perform any transformations if undef84# operands are involved.85 86---87name: func-undefops88tracksRegLiveness: true89body: |90 ; CHECK-LABEL: name: func-undefops91 ; CHECK: bb.0:92 ; CHECK: successors: %bb.2(0x40000000), %bb.1(0x40000000)93 ; CHECK: Bcc %bb.2, 1 /* CC::ne */, undef $cpsr94 ; CHECK: bb.1:95 ; CHECK: successors: %bb.3(0x80000000)96 ; CHECK: [[VMOVRS:%[0-9]+]]:gpr = VMOVRS undef %1:spr, 14 /* CC::al */, $noreg97 ; CHECK: B %bb.398 ; CHECK: bb.2:99 ; CHECK: successors: %bb.3(0x80000000)100 ; CHECK: [[VMOVRS1:%[0-9]+]]:gpr = VMOVRS undef %3:spr, 14 /* CC::al */, $noreg101 ; CHECK: bb.3:102 ; CHECK: [[PHI:%[0-9]+]]:gpr = PHI [[VMOVRS]], %bb.1, [[VMOVRS1]], %bb.2103 ; CHECK: [[VMOVSR:%[0-9]+]]:spr = VMOVSR [[PHI]], 14 /* CC::al */, $noreg104 bb.0:105 Bcc %bb.2, 1, undef $cpsr106 107 bb.1:108 %0:gpr = VMOVRS undef %1:spr, 14, $noreg109 B %bb.3110 111 bb.2:112 %2:gpr = VMOVRS undef %3:spr, 14, $noreg113 114 bb.3:115 %4:gpr = PHI %0, %bb.1, %2, %bb.2116 %5:spr = VMOVSR %4, 14, $noreg117...118