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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s3; Implement ctpop with vcnt4 5define <8 x i8> @vcnt8(ptr %A) nounwind {6; CHECK-LABEL: vcnt8:7; CHECK: @ %bb.0:8; CHECK-NEXT: vldr d16, [r0]9; CHECK-NEXT: vcnt.8 d16, d1610; CHECK-NEXT: vmov r0, r1, d1611; CHECK-NEXT: mov pc, lr12 %tmp1 = load <8 x i8>, ptr %A13 %tmp2 = call <8 x i8> @llvm.ctpop.v8i8(<8 x i8> %tmp1)14 ret <8 x i8> %tmp215}16 17define <16 x i8> @vcntQ8(ptr %A) nounwind {18; CHECK-LABEL: vcntQ8:19; CHECK: @ %bb.0:20; CHECK-NEXT: vld1.64 {d16, d17}, [r0]21; CHECK-NEXT: vcnt.8 q8, q822; CHECK-NEXT: vmov r0, r1, d1623; CHECK-NEXT: vmov r2, r3, d1724; CHECK-NEXT: mov pc, lr25 %tmp1 = load <16 x i8>, ptr %A26 %tmp2 = call <16 x i8> @llvm.ctpop.v16i8(<16 x i8> %tmp1)27 ret <16 x i8> %tmp228}29 30define <4 x i16> @vcnt16(ptr %A) nounwind {31; CHECK-LABEL: vcnt16:32; CHECK: @ %bb.0:33; CHECK-NEXT: vldr d16, [r0]34; CHECK-NEXT: vcnt.8 d16, d1635; CHECK-NEXT: vpaddl.u8 d16, d1636; CHECK-NEXT: vmov r0, r1, d1637; CHECK-NEXT: mov pc, lr38 %tmp1 = load <4 x i16>, ptr %A39 %tmp2 = call <4 x i16> @llvm.ctpop.v4i16(<4 x i16> %tmp1)40 ret <4 x i16> %tmp241}42 43define <8 x i16> @vcntQ16(ptr %A) nounwind {44; CHECK-LABEL: vcntQ16:45; CHECK: @ %bb.0:46; CHECK-NEXT: vld1.64 {d16, d17}, [r0]47; CHECK-NEXT: vcnt.8 q8, q848; CHECK-NEXT: vpaddl.u8 q8, q849; CHECK-NEXT: vmov r0, r1, d1650; CHECK-NEXT: vmov r2, r3, d1751; CHECK-NEXT: mov pc, lr52 %tmp1 = load <8 x i16>, ptr %A53 %tmp2 = call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %tmp1)54 ret <8 x i16> %tmp255}56 57define <2 x i32> @vcnt32(ptr %A) nounwind {58; CHECK-LABEL: vcnt32:59; CHECK: @ %bb.0:60; CHECK-NEXT: vldr d16, [r0]61; CHECK-NEXT: vcnt.8 d16, d1662; CHECK-NEXT: vpaddl.u8 d16, d1663; CHECK-NEXT: vpaddl.u16 d16, d1664; CHECK-NEXT: vmov r0, r1, d1665; CHECK-NEXT: mov pc, lr66 %tmp1 = load <2 x i32>, ptr %A67 %tmp2 = call <2 x i32> @llvm.ctpop.v2i32(<2 x i32> %tmp1)68 ret <2 x i32> %tmp269}70 71define <4 x i32> @vcntQ32(ptr %A) nounwind {72; CHECK-LABEL: vcntQ32:73; CHECK: @ %bb.0:74; CHECK-NEXT: vld1.64 {d16, d17}, [r0]75; CHECK-NEXT: vcnt.8 q8, q876; CHECK-NEXT: vpaddl.u8 q8, q877; CHECK-NEXT: vpaddl.u16 q8, q878; CHECK-NEXT: vmov r0, r1, d1679; CHECK-NEXT: vmov r2, r3, d1780; CHECK-NEXT: mov pc, lr81 %tmp1 = load <4 x i32>, ptr %A82 %tmp2 = call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %tmp1)83 ret <4 x i32> %tmp284}85 86define <1 x i64> @vcnt64(ptr %A) nounwind {87; CHECK-LABEL: vcnt64:88; CHECK: @ %bb.0:89; CHECK-NEXT: vldr d16, [r0]90; CHECK-NEXT: vcnt.8 d16, d1691; CHECK-NEXT: vpaddl.u8 d16, d1692; CHECK-NEXT: vpaddl.u16 d16, d1693; CHECK-NEXT: vpaddl.u32 d16, d1694; CHECK-NEXT: vmov r0, r1, d1695; CHECK-NEXT: mov pc, lr96 %tmp1 = load <1 x i64>, ptr %A97 %tmp2 = call <1 x i64> @llvm.ctpop.v1i64(<1 x i64> %tmp1)98 ret <1 x i64> %tmp299}100 101define <2 x i64> @vcntQ64(ptr %A) nounwind {102; CHECK-LABEL: vcntQ64:103; CHECK: @ %bb.0:104; CHECK-NEXT: vld1.64 {d16, d17}, [r0]105; CHECK-NEXT: vcnt.8 q8, q8106; CHECK-NEXT: vpaddl.u8 q8, q8107; CHECK-NEXT: vpaddl.u16 q8, q8108; CHECK-NEXT: vpaddl.u32 q8, q8109; CHECK-NEXT: vmov r0, r1, d16110; CHECK-NEXT: vmov r2, r3, d17111; CHECK-NEXT: mov pc, lr112 %tmp1 = load <2 x i64>, ptr %A113 %tmp2 = call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %tmp1)114 ret <2 x i64> %tmp2115}116 117declare <8 x i8> @llvm.ctpop.v8i8(<8 x i8>) nounwind readnone118declare <16 x i8> @llvm.ctpop.v16i8(<16 x i8>) nounwind readnone119declare <4 x i16> @llvm.ctpop.v4i16(<4 x i16>) nounwind readnone120declare <8 x i16> @llvm.ctpop.v8i16(<8 x i16>) nounwind readnone121declare <2 x i32> @llvm.ctpop.v2i32(<2 x i32>) nounwind readnone122declare <4 x i32> @llvm.ctpop.v4i32(<4 x i32>) nounwind readnone123declare <1 x i64> @llvm.ctpop.v1i64(<1 x i64>) nounwind readnone124declare <2 x i64> @llvm.ctpop.v2i64(<2 x i64>) nounwind readnone125 126define <8 x i8> @vclz8(ptr %A) nounwind {127; CHECK-LABEL: vclz8:128; CHECK: @ %bb.0:129; CHECK-NEXT: vldr d16, [r0]130; CHECK-NEXT: vclz.i8 d16, d16131; CHECK-NEXT: vmov r0, r1, d16132; CHECK-NEXT: mov pc, lr133 %tmp1 = load <8 x i8>, ptr %A134 %tmp2 = call <8 x i8> @llvm.ctlz.v8i8(<8 x i8> %tmp1, i1 0)135 ret <8 x i8> %tmp2136}137 138define <4 x i16> @vclz16(ptr %A) nounwind {139; CHECK-LABEL: vclz16:140; CHECK: @ %bb.0:141; CHECK-NEXT: vldr d16, [r0]142; CHECK-NEXT: vclz.i16 d16, d16143; CHECK-NEXT: vmov r0, r1, d16144; CHECK-NEXT: mov pc, lr145 %tmp1 = load <4 x i16>, ptr %A146 %tmp2 = call <4 x i16> @llvm.ctlz.v4i16(<4 x i16> %tmp1, i1 0)147 ret <4 x i16> %tmp2148}149 150define <2 x i32> @vclz32(ptr %A) nounwind {151; CHECK-LABEL: vclz32:152; CHECK: @ %bb.0:153; CHECK-NEXT: vldr d16, [r0]154; CHECK-NEXT: vclz.i32 d16, d16155; CHECK-NEXT: vmov r0, r1, d16156; CHECK-NEXT: mov pc, lr157 %tmp1 = load <2 x i32>, ptr %A158 %tmp2 = call <2 x i32> @llvm.ctlz.v2i32(<2 x i32> %tmp1, i1 0)159 ret <2 x i32> %tmp2160}161 162define <16 x i8> @vclzQ8(ptr %A) nounwind {163; CHECK-LABEL: vclzQ8:164; CHECK: @ %bb.0:165; CHECK-NEXT: vld1.64 {d16, d17}, [r0]166; CHECK-NEXT: vclz.i8 q8, q8167; CHECK-NEXT: vmov r0, r1, d16168; CHECK-NEXT: vmov r2, r3, d17169; CHECK-NEXT: mov pc, lr170 %tmp1 = load <16 x i8>, ptr %A171 %tmp2 = call <16 x i8> @llvm.ctlz.v16i8(<16 x i8> %tmp1, i1 0)172 ret <16 x i8> %tmp2173}174 175define <8 x i16> @vclzQ16(ptr %A) nounwind {176; CHECK-LABEL: vclzQ16:177; CHECK: @ %bb.0:178; CHECK-NEXT: vld1.64 {d16, d17}, [r0]179; CHECK-NEXT: vclz.i16 q8, q8180; CHECK-NEXT: vmov r0, r1, d16181; CHECK-NEXT: vmov r2, r3, d17182; CHECK-NEXT: mov pc, lr183 %tmp1 = load <8 x i16>, ptr %A184 %tmp2 = call <8 x i16> @llvm.ctlz.v8i16(<8 x i16> %tmp1, i1 0)185 ret <8 x i16> %tmp2186}187 188define <4 x i32> @vclzQ32(ptr %A) nounwind {189; CHECK-LABEL: vclzQ32:190; CHECK: @ %bb.0:191; CHECK-NEXT: vld1.64 {d16, d17}, [r0]192; CHECK-NEXT: vclz.i32 q8, q8193; CHECK-NEXT: vmov r0, r1, d16194; CHECK-NEXT: vmov r2, r3, d17195; CHECK-NEXT: mov pc, lr196 %tmp1 = load <4 x i32>, ptr %A197 %tmp2 = call <4 x i32> @llvm.ctlz.v4i32(<4 x i32> %tmp1, i1 0)198 ret <4 x i32> %tmp2199}200 201declare <8 x i8> @llvm.ctlz.v8i8(<8 x i8>, i1) nounwind readnone202declare <4 x i16> @llvm.ctlz.v4i16(<4 x i16>, i1) nounwind readnone203declare <2 x i32> @llvm.ctlz.v2i32(<2 x i32>, i1) nounwind readnone204 205declare <16 x i8> @llvm.ctlz.v16i8(<16 x i8>, i1) nounwind readnone206declare <8 x i16> @llvm.ctlz.v8i16(<8 x i16>, i1) nounwind readnone207declare <4 x i32> @llvm.ctlz.v4i32(<4 x i32>, i1) nounwind readnone208 209define <8 x i8> @vclss8(ptr %A) nounwind {210; CHECK-LABEL: vclss8:211; CHECK: @ %bb.0:212; CHECK-NEXT: vldr d16, [r0]213; CHECK-NEXT: vcls.s8 d16, d16214; CHECK-NEXT: vmov r0, r1, d16215; CHECK-NEXT: mov pc, lr216 %tmp1 = load <8 x i8>, ptr %A217 %tmp2 = call <8 x i8> @llvm.arm.neon.vcls.v8i8(<8 x i8> %tmp1)218 ret <8 x i8> %tmp2219}220 221define <4 x i16> @vclss16(ptr %A) nounwind {222; CHECK-LABEL: vclss16:223; CHECK: @ %bb.0:224; CHECK-NEXT: vldr d16, [r0]225; CHECK-NEXT: vcls.s16 d16, d16226; CHECK-NEXT: vmov r0, r1, d16227; CHECK-NEXT: mov pc, lr228 %tmp1 = load <4 x i16>, ptr %A229 %tmp2 = call <4 x i16> @llvm.arm.neon.vcls.v4i16(<4 x i16> %tmp1)230 ret <4 x i16> %tmp2231}232 233define <2 x i32> @vclss32(ptr %A) nounwind {234; CHECK-LABEL: vclss32:235; CHECK: @ %bb.0:236; CHECK-NEXT: vldr d16, [r0]237; CHECK-NEXT: vcls.s32 d16, d16238; CHECK-NEXT: vmov r0, r1, d16239; CHECK-NEXT: mov pc, lr240 %tmp1 = load <2 x i32>, ptr %A241 %tmp2 = call <2 x i32> @llvm.arm.neon.vcls.v2i32(<2 x i32> %tmp1)242 ret <2 x i32> %tmp2243}244 245define <16 x i8> @vclsQs8(ptr %A) nounwind {246; CHECK-LABEL: vclsQs8:247; CHECK: @ %bb.0:248; CHECK-NEXT: vld1.64 {d16, d17}, [r0]249; CHECK-NEXT: vcls.s8 q8, q8250; CHECK-NEXT: vmov r0, r1, d16251; CHECK-NEXT: vmov r2, r3, d17252; CHECK-NEXT: mov pc, lr253 %tmp1 = load <16 x i8>, ptr %A254 %tmp2 = call <16 x i8> @llvm.arm.neon.vcls.v16i8(<16 x i8> %tmp1)255 ret <16 x i8> %tmp2256}257 258define <8 x i16> @vclsQs16(ptr %A) nounwind {259; CHECK-LABEL: vclsQs16:260; CHECK: @ %bb.0:261; CHECK-NEXT: vld1.64 {d16, d17}, [r0]262; CHECK-NEXT: vcls.s16 q8, q8263; CHECK-NEXT: vmov r0, r1, d16264; CHECK-NEXT: vmov r2, r3, d17265; CHECK-NEXT: mov pc, lr266 %tmp1 = load <8 x i16>, ptr %A267 %tmp2 = call <8 x i16> @llvm.arm.neon.vcls.v8i16(<8 x i16> %tmp1)268 ret <8 x i16> %tmp2269}270 271define <4 x i32> @vclsQs32(ptr %A) nounwind {272; CHECK-LABEL: vclsQs32:273; CHECK: @ %bb.0:274; CHECK-NEXT: vld1.64 {d16, d17}, [r0]275; CHECK-NEXT: vcls.s32 q8, q8276; CHECK-NEXT: vmov r0, r1, d16277; CHECK-NEXT: vmov r2, r3, d17278; CHECK-NEXT: mov pc, lr279 %tmp1 = load <4 x i32>, ptr %A280 %tmp2 = call <4 x i32> @llvm.arm.neon.vcls.v4i32(<4 x i32> %tmp1)281 ret <4 x i32> %tmp2282}283 284define i32 @ctpop8(i8 %x) nounwind readnone {285; CHECK-LABEL: ctpop8:286; CHECK: @ %bb.0:287; CHECK-NEXT: mov r1, #85288; CHECK-NEXT: and r1, r1, r0, lsr #1289; CHECK-NEXT: sub r0, r0, r1290; CHECK-NEXT: mov r1, #51291; CHECK-NEXT: and r1, r1, r0, lsr #2292; CHECK-NEXT: and r0, r0, #51293; CHECK-NEXT: add r0, r0, r1294; CHECK-NEXT: add r0, r0, r0, lsr #4295; CHECK-NEXT: and r0, r0, #15296; CHECK-NEXT: mov pc, lr297 %count = tail call i8 @llvm.ctpop.i8(i8 %x)298 %conv = zext i8 %count to i32299 ret i32 %conv300}301 302define i32 @ctpop16(i16 %x) nounwind readnone {303; CHECK-LABEL: ctpop16:304; CHECK: @ %bb.0:305; CHECK-NEXT: mov r1, #85306; CHECK-NEXT: orr r1, r1, #21760307; CHECK-NEXT: and r1, r1, r0, lsr #1308; CHECK-NEXT: sub r0, r0, r1309; CHECK-NEXT: mov r1, #51310; CHECK-NEXT: orr r1, r1, #13056311; CHECK-NEXT: and r2, r0, r1312; CHECK-NEXT: and r0, r1, r0, lsr #2313; CHECK-NEXT: add r0, r2, r0314; CHECK-NEXT: add r0, r0, r0, lsr #4315; CHECK-NEXT: and r1, r0, #3840316; CHECK-NEXT: and r0, r0, #15317; CHECK-NEXT: add r0, r0, r1, lsr #8318; CHECK-NEXT: mov pc, lr319 %count = tail call i16 @llvm.ctpop.i16(i16 %x)320 %conv = zext i16 %count to i32321 ret i32 %conv322}323 324define i32 @ctpop32(i32 %x) nounwind readnone {325; CHECK-LABEL: ctpop32:326; CHECK: @ %bb.0:327; CHECK-NEXT: ldr r1, .LCPI22_0328; CHECK-NEXT: ldr r2, .LCPI22_3329; CHECK-NEXT: and r1, r1, r0, lsr #1330; CHECK-NEXT: ldr r12, .LCPI22_1331; CHECK-NEXT: sub r0, r0, r1332; CHECK-NEXT: ldr r3, .LCPI22_2333; CHECK-NEXT: and r1, r0, r2334; CHECK-NEXT: and r0, r2, r0, lsr #2335; CHECK-NEXT: add r0, r1, r0336; CHECK-NEXT: add r0, r0, r0, lsr #4337; CHECK-NEXT: and r0, r0, r12338; CHECK-NEXT: mul r1, r0, r3339; CHECK-NEXT: lsr r0, r1, #24340; CHECK-NEXT: mov pc, lr341; CHECK-NEXT: .p2align 2342; CHECK-NEXT: @ %bb.1:343; CHECK-NEXT: .LCPI22_0:344; CHECK-NEXT: .long 1431655765 @ 0x55555555345; CHECK-NEXT: .LCPI22_1:346; CHECK-NEXT: .long 252645135 @ 0xf0f0f0f347; CHECK-NEXT: .LCPI22_2:348; CHECK-NEXT: .long 16843009 @ 0x1010101349; CHECK-NEXT: .LCPI22_3:350; CHECK-NEXT: .long 858993459 @ 0x33333333351 %count = tail call i32 @llvm.ctpop.i32(i32 %x)352 ret i32 %count353}354 355define i64 @ctpop64(i64 %x) nounwind readnone {356; CHECK-LABEL: ctpop64:357; CHECK: @ %bb.0:358; CHECK-NEXT: .save {r4, lr}359; CHECK-NEXT: push {r4, lr}360; CHECK-NEXT: ldr r2, .LCPI23_0361; CHECK-NEXT: ldr r3, .LCPI23_3362; CHECK-NEXT: and r4, r2, r0, lsr #1363; CHECK-NEXT: and r2, r2, r1, lsr #1364; CHECK-NEXT: sub r0, r0, r4365; CHECK-NEXT: sub r1, r1, r2366; CHECK-NEXT: and r4, r0, r3367; CHECK-NEXT: and r2, r1, r3368; CHECK-NEXT: and r0, r3, r0, lsr #2369; CHECK-NEXT: and r1, r3, r1, lsr #2370; CHECK-NEXT: add r0, r4, r0371; CHECK-NEXT: ldr lr, .LCPI23_1372; CHECK-NEXT: add r1, r2, r1373; CHECK-NEXT: ldr r12, .LCPI23_2374; CHECK-NEXT: add r0, r0, r0, lsr #4375; CHECK-NEXT: and r0, r0, lr376; CHECK-NEXT: add r1, r1, r1, lsr #4377; CHECK-NEXT: mul r2, r0, r12378; CHECK-NEXT: and r0, r1, lr379; CHECK-NEXT: mul r1, r0, r12380; CHECK-NEXT: lsr r0, r2, #24381; CHECK-NEXT: add r0, r0, r1, lsr #24382; CHECK-NEXT: mov r1, #0383; CHECK-NEXT: pop {r4, lr}384; CHECK-NEXT: mov pc, lr385; CHECK-NEXT: .p2align 2386; CHECK-NEXT: @ %bb.1:387; CHECK-NEXT: .LCPI23_0:388; CHECK-NEXT: .long 1431655765 @ 0x55555555389; CHECK-NEXT: .LCPI23_1:390; CHECK-NEXT: .long 252645135 @ 0xf0f0f0f391; CHECK-NEXT: .LCPI23_2:392; CHECK-NEXT: .long 16843009 @ 0x1010101393; CHECK-NEXT: .LCPI23_3:394; CHECK-NEXT: .long 858993459 @ 0x33333333395 %count = tail call i64 @llvm.ctpop.i64(i64 %x)396 ret i64 %count397}398 399define i32 @ctpop_eq_one(i64 %x) nounwind readnone {400; CHECK-LABEL: ctpop_eq_one:401; CHECK: @ %bb.0:402; CHECK-NEXT: subs r2, r0, #1403; CHECK-NEXT: sbc r3, r1, #0404; CHECK-NEXT: eor r12, r1, r3405; CHECK-NEXT: eor r1, r0, r2406; CHECK-NEXT: subs r1, r2, r1407; CHECK-NEXT: mov r0, #0408; CHECK-NEXT: sbcs r1, r3, r12409; CHECK-NEXT: movlo r0, #1410; CHECK-NEXT: mov pc, lr411 %count = tail call i64 @llvm.ctpop.i64(i64 %x)412 %cmp = icmp eq i64 %count, 1413 %conv = zext i1 %cmp to i32414 ret i32 %conv415}416 417declare i8 @llvm.ctpop.i8(i8) nounwind readnone418declare i16 @llvm.ctpop.i16(i16) nounwind readnone419declare i32 @llvm.ctpop.i32(i32) nounwind readnone420declare i64 @llvm.ctpop.i64(i64) nounwind readnone421 422declare <8 x i8> @llvm.arm.neon.vcls.v8i8(<8 x i8>) nounwind readnone423declare <4 x i16> @llvm.arm.neon.vcls.v4i16(<4 x i16>) nounwind readnone424declare <2 x i32> @llvm.arm.neon.vcls.v2i32(<2 x i32>) nounwind readnone425 426declare <16 x i8> @llvm.arm.neon.vcls.v16i8(<16 x i8>) nounwind readnone427declare <8 x i16> @llvm.arm.neon.vcls.v8i16(<8 x i16>) nounwind readnone428declare <4 x i32> @llvm.arm.neon.vcls.v4i32(<4 x i32>) nounwind readnone429