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1; REQUIRES: asserts2; RUN: llc < %s -mtriple=thumbv8m.main-none-eabi -debug-only=machine-scheduler,post-RA-sched -print-before=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s3 4; CHECK-LABEL: test_misched5; Pre and post ra machine scheduling6; CHECK: ********** MI Scheduling **********7; CHECK: t2LDRi128; CHECK: Latency : 29; CHECK: ********** MI Scheduling **********10; CHECK: t2LDRi1211; CHECK: Latency : 212 13define i32 @test_misched(ptr %ptr) "target-cpu"="cortex-m33" {14entry:15 %l = load i32, ptr %ptr16 store i32 0, ptr %ptr17 ret i32 %l18}19 20; CHECK-LABEL: test_rasched21; CHECK: Subtarget disables post-MI-sched.22; CHECK: ********** List Scheduling **********23 24define i32 @test_rasched(ptr %ptr) {25entry:26 %l = load i32, ptr %ptr27 store i32 0, ptr %ptr28 ret i32 %l29}30 31