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1; RUN: llc < %s -mtriple=armv5te | FileCheck %s --check-prefix=V52; RUN: llc < %s -mtriple=armv6 | FileCheck %s --check-prefix=V63; RUN: llc < %s -mtriple=armv6t2 | FileCheck %s --check-prefix=V6T24; RUN: llc < %s -mtriple=armv7 | FileCheck %s --check-prefix=V75; PR183646 7define i64 @f() #0 {8entry:9; V5-NOT: movw10; V6-NOT: movw11; V6T2: movw12; V7: movw13 %y = alloca i64, align 814 %z = alloca i64, align 815 store i64 1, ptr %y, align 816 store i64 11579764786944, ptr %z, align 817 %0 = load i64, ptr %y, align 818 %1 = load i64, ptr %z, align 819 %sub = sub i64 %0, %120 ret i64 %sub21}22 23define i64 @g(i64 %a, i32 %b) #0 {24entry:25; V5-NOT: movw26; V6-NOT: movw27; V6T2: movw28; V7: movw29 %0 = mul i64 %a, 8640000030 %mul = add i64 %0, -21086680320000031 %conv = sext i32 %b to i6432 %add = add nsw i64 %mul, %conv33 ret i64 %add34}35