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1; RUN: llc < %s -mtriple=arm-apple-ios -mcpu=cortex-a8 -arm-atomic-cfg-tidy=0 | FileCheck %s2; RUN: llc < %s -mtriple=arm-apple-ios -mcpu=cortex-a8 -arm-atomic-cfg-tidy=0 -regalloc=basic | FileCheck %s3; Implementing vld / vst as REG_SEQUENCE eliminates the extra vmov's.4 5%struct.int16x8_t = type { <8 x i16> }6%struct.int32x4_t = type { <4 x i32> }7%struct.__neon_int8x8x2_t = type { <8 x i8>, <8 x i8> }8%struct.__neon_int8x8x3_t = type { <8 x i8>, <8 x i8>, <8 x i8> }9%struct.__neon_int16x8x2_t = type { <8 x i16>, <8 x i16> }10%struct.__neon_int32x4x2_t = type { <4 x i32>, <4 x i32> }11 12define void @t1(ptr %i_ptr, ptr %o_ptr, ptr nocapture %vT0ptr, ptr nocapture %vT1ptr) nounwind {13entry:14; CHECK-LABEL: t1:15; CHECK: vld1.1616; CHECK-NOT: vmov d17; CHECK: vmovl.s1618; CHECK: vshrn.i3219; CHECK: vshrn.i3220; CHECK-NOT: vmov d21; CHECK-NEXT: vst1.1622 %0 = getelementptr inbounds %struct.int32x4_t, ptr %vT0ptr, i32 0, i32 0 ; <ptr> [#uses=1]23 %1 = load <4 x i32>, ptr %0, align 16 ; <<4 x i32>> [#uses=1]24 %2 = getelementptr inbounds %struct.int32x4_t, ptr %vT1ptr, i32 0, i32 0 ; <ptr> [#uses=1]25 %3 = load <4 x i32>, ptr %2, align 16 ; <<4 x i32>> [#uses=1]26 %4 = tail call <8 x i16> @llvm.arm.neon.vld1.v8i16.p0(ptr %i_ptr, i32 1) ; <<8 x i16>> [#uses=1]27 %5 = bitcast <8 x i16> %4 to <2 x double> ; <<2 x double>> [#uses=2]28 %6 = extractelement <2 x double> %5, i32 0 ; <double> [#uses=1]29 %7 = bitcast double %6 to <4 x i16> ; <<4 x i16>> [#uses=1]30 %8 = sext <4 x i16> %7 to <4 x i32> ; <<4 x i32>> [#uses=1]31 %9 = extractelement <2 x double> %5, i32 1 ; <double> [#uses=1]32 %10 = bitcast double %9 to <4 x i16> ; <<4 x i16>> [#uses=1]33 %11 = sext <4 x i16> %10 to <4 x i32> ; <<4 x i32>> [#uses=1]34 %12 = mul <4 x i32> %1, %8 ; <<4 x i32>> [#uses=1]35 %13 = mul <4 x i32> %3, %11 ; <<4 x i32>> [#uses=1]36 %14 = lshr <4 x i32> %12, <i32 12, i32 12, i32 12, i32 12>37 %trunc_15 = trunc <4 x i32> %14 to <4 x i16>38 %15 = lshr <4 x i32> %13, <i32 12, i32 12, i32 12, i32 12>39 %trunc_16 = trunc <4 x i32> %15 to <4 x i16>40 %16 = shufflevector <4 x i16> %trunc_15, <4 x i16> %trunc_16, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> ; <<8 x i16>> [#uses=1]41 tail call void @llvm.arm.neon.vst1.p0.v8i16(ptr %o_ptr, <8 x i16> %16, i32 1)42 ret void43}44 45define void @t2(ptr %i_ptr, ptr %o_ptr, ptr nocapture %vT0ptr, ptr nocapture %vT1ptr) nounwind {46entry:47; CHECK-LABEL: t2:48; CHECK: vld1.1649; CHECK-NOT: vmov50; CHECK: vmul.i1651; CHECK: vld1.1652; CHECK: vmul.i1653; CHECK-NOT: vmov54; CHECK: vst1.1655; CHECK: vst1.1656 %0 = getelementptr inbounds %struct.int16x8_t, ptr %vT0ptr, i32 0, i32 0 ; <ptr> [#uses=1]57 %1 = load <8 x i16>, ptr %0, align 16 ; <<8 x i16>> [#uses=1]58 %2 = getelementptr inbounds %struct.int16x8_t, ptr %vT1ptr, i32 0, i32 0 ; <ptr> [#uses=1]59 %3 = load <8 x i16>, ptr %2, align 16 ; <<8 x i16>> [#uses=1]60 %4 = tail call <8 x i16> @llvm.arm.neon.vld1.v8i16.p0(ptr %i_ptr, i32 1) ; <<8 x i16>> [#uses=1]61 %5 = getelementptr inbounds i16, ptr %i_ptr, i32 8 ; <ptr> [#uses=1]62 %6 = tail call <8 x i16> @llvm.arm.neon.vld1.v8i16.p0(ptr %5, i32 1) ; <<8 x i16>> [#uses=1]63 %7 = mul <8 x i16> %1, %4 ; <<8 x i16>> [#uses=1]64 %8 = mul <8 x i16> %3, %6 ; <<8 x i16>> [#uses=1]65 tail call void @llvm.arm.neon.vst1.p0.v8i16(ptr %o_ptr, <8 x i16> %7, i32 1)66 %9 = getelementptr inbounds i16, ptr %o_ptr, i32 8 ; <ptr> [#uses=1]67 tail call void @llvm.arm.neon.vst1.p0.v8i16(ptr %9, <8 x i16> %8, i32 1)68 ret void69}70 71define <8 x i8> @t3(ptr %A, ptr %B) nounwind {72; CHECK-LABEL: t3:73; CHECK: vld3.874; CHECK: vmul.i875; CHECK: vmov r76; CHECK-NOT: vmov d77; CHECK: vst3.878 %tmp1 = call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8.p0(ptr %A, i32 1) ; <%struct.__neon_int8x8x3_t> [#uses=2]79 %tmp2 = extractvalue %struct.__neon_int8x8x3_t %tmp1, 0 ; <<8 x i8>> [#uses=1]80 %tmp3 = extractvalue %struct.__neon_int8x8x3_t %tmp1, 2 ; <<8 x i8>> [#uses=1]81 %tmp4 = extractvalue %struct.__neon_int8x8x3_t %tmp1, 1 ; <<8 x i8>> [#uses=1]82 %tmp5 = sub <8 x i8> %tmp3, %tmp483 %tmp6 = add <8 x i8> %tmp2, %tmp3 ; <<8 x i8>> [#uses=1]84 %tmp7 = mul <8 x i8> %tmp4, %tmp285 tail call void @llvm.arm.neon.vst3.p0.v8i8(ptr %B, <8 x i8> %tmp5, <8 x i8> %tmp6, <8 x i8> %tmp7, i32 1)86 ret <8 x i8> %tmp487}88 89define void @t4(ptr %in, ptr %out) nounwind {90entry:91; CHECK-LABEL: t4:92; CHECK: vld2.3293; CHECK-NOT: vmov94; CHECK: vld2.3295; CHECK-NOT: vmov96; CHECK: bne97 %tmp2 = tail call %struct.__neon_int32x4x2_t @llvm.arm.neon.vld2.v4i32.p0(ptr %in, i32 1) ; <%struct.__neon_int32x4x2_t> [#uses=2]98 %tmp3 = getelementptr inbounds i32, ptr %in, i32 8 ; <ptr> [#uses=1]99 %tmp5 = tail call %struct.__neon_int32x4x2_t @llvm.arm.neon.vld2.v4i32.p0(ptr %tmp3, i32 1) ; <%struct.__neon_int32x4x2_t> [#uses=2]100 br i1 undef, label %return1, label %return2101 102return1:103; CHECK: %return1104; CHECK-NOT: vmov105; CHECK-NEXT: vadd.i32106; CHECK-NEXT: vadd.i32107; CHECK-NEXT: vst2.32108 %tmp52 = extractvalue %struct.__neon_int32x4x2_t %tmp2, 0 ; <<4 x i32>> [#uses=1]109 %tmp57 = extractvalue %struct.__neon_int32x4x2_t %tmp2, 1 ; <<4 x i32>> [#uses=1]110 %tmp = extractvalue %struct.__neon_int32x4x2_t %tmp5, 0 ; <<4 x i32>> [#uses=1]111 %tmp39 = extractvalue %struct.__neon_int32x4x2_t %tmp5, 1 ; <<4 x i32>> [#uses=1]112 %tmp6 = add <4 x i32> %tmp52, %tmp ; <<4 x i32>> [#uses=1]113 %tmp7 = add <4 x i32> %tmp57, %tmp39 ; <<4 x i32>> [#uses=1]114 tail call void @llvm.arm.neon.vst2.p0.v4i32(ptr %out, <4 x i32> %tmp6, <4 x i32> %tmp7, i32 1)115 ret void116 117return2:118; CHECK: %return2119; CHECK: vadd.i32120; CHECK-NOT: vmov121; CHECK: vst2.32 {d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}}}122 %tmp100 = extractvalue %struct.__neon_int32x4x2_t %tmp2, 0 ; <<4 x i32>> [#uses=1]123 %tmp101 = extractvalue %struct.__neon_int32x4x2_t %tmp5, 1 ; <<4 x i32>> [#uses=1]124 %tmp102 = add <4 x i32> %tmp100, %tmp101 ; <<4 x i32>> [#uses=1]125 tail call void @llvm.arm.neon.vst2.p0.v4i32(ptr %out, <4 x i32> %tmp102, <4 x i32> %tmp101, i32 1)126 call void @llvm.trap()127 unreachable128}129 130define <8 x i16> @t5(ptr %A, ptr %B) nounwind {131; CHECK-LABEL: t5:132; CHECK: vld1.32133; How can FileCheck match Q and D registers? We need a lisp interpreter.134; CHECK: vorr {{q[0-9]+}}, {{q[0-9]+}}, {{q[0-9]+}}135; CHECK-NOT: vmov136; CHECK: vld2.16 {d{{[0-9]+}}[1], d{{[0-9]+}}[1]}, [r0]137; CHECK-NOT: vmov138; CHECK: vadd.i16139 %tmp1 = load <8 x i16>, ptr %B ; <<8 x i16>> [#uses=2]140 %tmp2 = call %struct.__neon_int16x8x2_t @llvm.arm.neon.vld2lane.v8i16.p0(ptr %A, <8 x i16> %tmp1, <8 x i16> %tmp1, i32 1, i32 1) ; <%struct.__neon_int16x8x2_t> [#uses=2]141 %tmp3 = extractvalue %struct.__neon_int16x8x2_t %tmp2, 0 ; <<8 x i16>> [#uses=1]142 %tmp4 = extractvalue %struct.__neon_int16x8x2_t %tmp2, 1 ; <<8 x i16>> [#uses=1]143 %tmp5 = add <8 x i16> %tmp3, %tmp4 ; <<8 x i16>> [#uses=1]144 ret <8 x i16> %tmp5145}146 147define <8 x i8> @t6(ptr %A, ptr %B) nounwind {148; CHECK-LABEL: t6:149; CHECK: vldr150; CHECK: vorr d[[D0:[0-9]+]], d[[D1:[0-9]+]]151; CHECK-NEXT: vld2.8 {d[[D1]][1], d[[D0]][1]}152 %tmp1 = load <8 x i8>, ptr %B ; <<8 x i8>> [#uses=2]153 %tmp2 = call %struct.__neon_int8x8x2_t @llvm.arm.neon.vld2lane.v8i8.p0(ptr %A, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 1, i32 1) ; <%struct.__neon_int8x8x2_t> [#uses=2]154 %tmp3 = extractvalue %struct.__neon_int8x8x2_t %tmp2, 0 ; <<8 x i8>> [#uses=1]155 %tmp4 = extractvalue %struct.__neon_int8x8x2_t %tmp2, 1 ; <<8 x i8>> [#uses=1]156 %tmp5 = add <8 x i8> %tmp3, %tmp4 ; <<8 x i8>> [#uses=1]157 ret <8 x i8> %tmp5158}159 160define void @t7(ptr %iptr, ptr %optr) nounwind {161entry:162; CHECK-LABEL: t7:163; CHECK: vld2.32164; CHECK: vst2.32165; CHECK: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}},166; CHECK: vorr q[[Q0:[0-9]+]], q[[Q1:[0-9]+]], q[[Q1:[0-9]+]]167; CHECK-NOT: vmov168; CHECK: vuzp.32 q[[Q1]], q[[Q0]]169; CHECK: vst1.32170 %0 = tail call %struct.__neon_int32x4x2_t @llvm.arm.neon.vld2.v4i32.p0(ptr %iptr, i32 1) ; <%struct.__neon_int32x4x2_t> [#uses=2]171 %tmp57 = extractvalue %struct.__neon_int32x4x2_t %0, 0 ; <<4 x i32>> [#uses=1]172 %tmp60 = extractvalue %struct.__neon_int32x4x2_t %0, 1 ; <<4 x i32>> [#uses=1]173 tail call void @llvm.arm.neon.vst2.p0.v4i32(ptr %optr, <4 x i32> %tmp57, <4 x i32> %tmp60, i32 1)174 %1 = tail call <4 x i32> @llvm.arm.neon.vld1.v4i32.p0(ptr %iptr, i32 1) ; <<4 x i32>> [#uses=1]175 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 0, i32 2, i32 0, i32 2> ; <<4 x i32>> [#uses=1]176 tail call void @llvm.arm.neon.vst1.p0.v4i32(ptr %optr, <4 x i32> %2, i32 1)177 ret void178}179 180; PR7156181define arm_aapcs_vfpcc i32 @t8() nounwind {182; CHECK-LABEL: t8:183; CHECK: vrsqrte.f32 q8, q8184bb.nph55.bb.nph55.split_crit_edge:185 br label %bb3186 187bb3: ; preds = %bb3, %bb.nph55.bb.nph55.split_crit_edge188 br i1 undef, label %bb5, label %bb3189 190bb5: ; preds = %bb3191 br label %bb.i25192 193bb.i25: ; preds = %bb.i25, %bb5194 %0 = shufflevector <2 x float> undef, <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3> ; <<4 x float>> [#uses=1]195 %1 = call <4 x float> @llvm.arm.neon.vrsqrte.v4f32(<4 x float> %0) nounwind ; <<4 x float>> [#uses=1]196 %2 = fmul <4 x float> %1, %1 ; <<4 x float>> [#uses=1]197 %3 = fmul <4 x float> %2, %2 ; <<4 x float>> [#uses=1]198 %tmp26.i = bitcast <4 x float> %3 to <2 x double> ; <<2 x double>> [#uses=1]199 %4 = extractelement <2 x double> %tmp26.i, i32 0 ; <double> [#uses=1]200 %5 = bitcast double %4 to <2 x float> ; <<2 x float>> [#uses=1]201 %6 = extractelement <2 x float> %5, i32 1 ; <float> [#uses=1]202 store float %6, ptr undef, align 4203 br i1 undef, label %bb6, label %bb.i25204 205bb6: ; preds = %bb.i25206 br i1 undef, label %bb7, label %bb14207 208bb7: ; preds = %bb6209 br label %bb.i49210 211bb.i49: ; preds = %bb.i49, %bb7212 br i1 undef, label %bb.i19, label %bb.i49213 214bb.i19: ; preds = %bb.i19, %bb.i49215 br i1 undef, label %exit, label %bb.i19216 217exit: ; preds = %bb.i19218 unreachable219 220bb14: ; preds = %bb6221 ret i32 0222}223 224%0 = type { %1, %1, %1, %1 }225%1 = type { %2 }226%2 = type { <4 x float> }227%3 = type { %0, %1 }228 229; PR7157230define arm_aapcs_vfpcc float @t9(ptr nocapture, ptr nocapture) nounwind {231; CHECK-LABEL: t9:232; CHECK: vmov.i32 d16, #0x0233; CHECK-NEXT: vst1.64 {d16, d17}, [r0:128]234; CHECK-NEXT: vorr d17, d16, d16235; CHECK-NEXT: vst1.64 {d16, d17}, [r0:128]236 %3 = bitcast double 0.000000e+00 to <2 x float> ; <<2 x float>> [#uses=2]237 %4 = shufflevector <2 x float> %3, <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3> ; <<4 x float>> [#uses=1]238 store <4 x float> %4, ptr undef, align 16239 %5 = shufflevector <2 x float> %3, <2 x float> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 2, i32 3> ; <<4 x float>> [#uses=1]240 store <4 x float> %5, ptr undef, align 16241 br label %8242 243; <label>:6 ; preds = %8244 br label %7245 246; <label>:7 ; preds = %6247 br label %8248 249; <label>:8 ; preds = %7, %2250 br label %6251 252; <label>:9 ; preds = %8253 ret float undef254 255; <label>:10 ; preds = %6256 ret float 9.990000e+02257}258 259; PR7162260define arm_aapcs_vfpcc i32 @t10(float %x) nounwind {261; CHECK-LABEL: t10:262; CHECK: vmov.i32 [[Q9:q[0-9]+]], #0x3f000000263; CHECK: vmul.f32 [[Q8:q[0-9]+]], [[Q0:q[0-9]+]], [[Q0]]264; CHECK-NEXT: vadd.f32 [[Q8]], [[Q8]], [[Q8]]265; CHECK-NEXT: vadd.f32 [[Q1:q[0-9]+]], [[Q8]], [[Q8]]266; CHECK-NEXT: vmul.f32 [[Q8]], [[Q9]], d1[0]267; CHECK-NEXT: vmul.f32 [[Q8]], [[Q8]], [[Q8]]268; CHECK-NEXT: vadd.f32 [[Q8]], [[Q8]], [[Q8]]269; CHECK-NEXT: vmul.f32 [[Q8]], [[Q8]], [[Q8]]270; CHECK-NEXT: vst1.32 {d17[1]}, [r0:32]271; CHECK-NEXT: mov r0, #0272; CHECK-NEXT: cmp r0, #0273; CHECK-NEXT: bxne lr274; CHECK-NEXT: LBB9_1:275; CHECK-NEXT: trap276entry:277 %0 = shufflevector <4 x float> zeroinitializer, <4 x float> undef, <4 x i32> zeroinitializer ; <<4 x float>> [#uses=1]278 %1 = insertelement <4 x float> %0, float %x, i32 1 ; <<4 x float>> [#uses=1]279 %2 = insertelement <4 x float> %1, float %x, i32 2 ; <<4 x float>> [#uses=1]280 %3 = insertelement <4 x float> %2, float %x, i32 3 ; <<4 x float>> [#uses=1]281 %tmp54.i = bitcast <4 x float> %3 to <2 x double> ; <<2 x double>> [#uses=1]282 %4 = extractelement <2 x double> %tmp54.i, i32 1 ; <double> [#uses=1]283 %5 = bitcast double %4 to <2 x float> ; <<2 x float>> [#uses=1]284 %6 = shufflevector <2 x float> %5, <2 x float> undef, <4 x i32> zeroinitializer ; <<4 x float>> [#uses=1]285 %7 = fmul <4 x float> %6, %6 286 %8 = fadd <4 x float> %7, %7287 %9 = fadd <4 x float> %8, %8288 %10 = shufflevector <4 x float> undef, <4 x float> %9, <4 x i32> <i32 0, i32 1, i32 2, i32 7> ; <<4 x float>> [#uses=1]289 %11 = fmul <4 x float> %10, <float 5.000000e-01, float 5.000000e-01, float 5.000000e-01, float 5.000000e-01> ; <<4 x float>> [#uses=1]290 %12 = shufflevector <4 x float> %11, <4 x float> undef, <4 x i32> <i32 3, i32 undef, i32 undef, i32 undef> ; <<4 x float>> [#uses=1]291 %13 = shufflevector <4 x float> %12, <4 x float> undef, <4 x i32> zeroinitializer ; <<4 x float>> [#uses=1]292 %14 = fmul <4 x float> %13, %13293 %15 = fadd <4 x float> %14, %14294 %16 = shufflevector <4 x float> undef, <4 x float> %15, <4 x i32> <i32 0, i32 1, i32 6, i32 3> ; <<4 x float>> [#uses=1]295 %17 = fmul <4 x float> %16, %16296 %18 = extractelement <4 x float> %17, i32 2 ; <float> [#uses=1]297 store float %18, ptr undef, align 4298 br i1 undef, label %exit, label %bb14299 300exit: ; preds = %bb.i19301 unreachable302 303bb14: ; preds = %bb6304 ret i32 0305}306 307; This test crashes the coalescer because live variables were not updated properly.308define <8 x i8> @t11(ptr %A1, ptr %A2, ptr %A3, ptr %A4, ptr %A5, ptr %A6, ptr %A7, ptr %A8, ptr %B) nounwind {309 %tmp1d = call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8.p0(ptr %A4, i32 1) ; <%struct.__neon_int8x8x3_t> [#uses=1]310 %tmp2d = extractvalue %struct.__neon_int8x8x3_t %tmp1d, 0 ; <<8 x i8>> [#uses=1]311 %tmp1f = call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8.p0(ptr %A6, i32 1) ; <%struct.__neon_int8x8x3_t> [#uses=1]312 %tmp2f = extractvalue %struct.__neon_int8x8x3_t %tmp1f, 0 ; <<8 x i8>> [#uses=1]313 %tmp2bd = add <8 x i8> zeroinitializer, %tmp2d ; <<8 x i8>> [#uses=1]314 %tmp2abcd = mul <8 x i8> zeroinitializer, %tmp2bd ; <<8 x i8>> [#uses=1]315 %tmp2ef = sub <8 x i8> zeroinitializer, %tmp2f ; <<8 x i8>> [#uses=1]316 %tmp2efgh = mul <8 x i8> %tmp2ef, undef ; <<8 x i8>> [#uses=2]317 call void @llvm.arm.neon.vst3.p0.v8i8(ptr %A2, <8 x i8> undef, <8 x i8> undef, <8 x i8> %tmp2efgh, i32 1)318 %tmp2 = sub <8 x i8> %tmp2efgh, %tmp2abcd ; <<8 x i8>> [#uses=1]319 %tmp7 = mul <8 x i8> undef, %tmp2 ; <<8 x i8>> [#uses=1]320 tail call void @llvm.arm.neon.vst3.p0.v8i8(ptr %B, <8 x i8> undef, <8 x i8> undef, <8 x i8> %tmp7, i32 1)321 ret <8 x i8> undef322}323 324declare <4 x i32> @llvm.arm.neon.vld1.v4i32.p0(ptr, i32) nounwind readonly325 326declare <8 x i16> @llvm.arm.neon.vld1.v8i16.p0(ptr, i32) nounwind readonly327 328declare <4 x i16> @llvm.arm.neon.vshiftn.v4i16(<4 x i32>, <4 x i32>) nounwind readnone329 330declare void @llvm.arm.neon.vst1.p0.v4i32(ptr, <4 x i32>, i32) nounwind331 332declare void @llvm.arm.neon.vst1.p0.v8i16(ptr, <8 x i16>, i32) nounwind333 334declare void @llvm.arm.neon.vst3.p0.v8i8(ptr, <8 x i8>, <8 x i8>, <8 x i8>, i32)335nounwind336 337declare %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8.p0(ptr, i32) nounwind readonly338 339declare %struct.__neon_int32x4x2_t @llvm.arm.neon.vld2.v4i32.p0(ptr, i32) nounwind readonly340 341declare %struct.__neon_int8x8x2_t @llvm.arm.neon.vld2lane.v8i8.p0(ptr, <8 x i8>, <8 x i8>, i32, i32) nounwind readonly342 343declare %struct.__neon_int16x8x2_t @llvm.arm.neon.vld2lane.v8i16.p0(ptr, <8 x i16>, <8 x i16>, i32, i32) nounwind readonly344 345declare void @llvm.arm.neon.vst2.p0.v4i32(ptr, <4 x i32>, <4 x i32>, i32) nounwind346 347declare <4 x float> @llvm.arm.neon.vrsqrte.v4f32(<4 x float>) nounwind readnone348 349declare void @llvm.trap() nounwind350