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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=armv7-apple-ios -run-pass=regallocfast -o - %s | FileCheck %s3# RUN: llc -mtriple=armv7-apple-ios -passes=regallocfast -o - %s | FileCheck %s4 5 6# tBX_RET uses an implicit vreg with a sub-register. That implicit use will7# typically be rewritten as a use of the relevant super-register. Make sure8# regallocfast is able to process the remaining operands (here, %2) and rewrite9# them to use physical registers.10---11name: different_vreg12tracksRegLiveness: true13body: |14 bb.0:15 liveins: $d2, $d4, $d716 17 ; CHECK-LABEL: name: different_vreg18 ; CHECK: liveins: $d2, $d4, $d719 ; CHECK-NEXT: {{ $}}20 ; CHECK-NEXT: renamable $d5 = COPY killed $d421 ; CHECK-NEXT: renamable $d4 = COPY killed $d222 ; CHECK-NEXT: undef renamable $d0 = COPY renamable $d5, implicit-def $q0_q123 ; CHECK-NEXT: renamable $d1 = COPY renamable $d424 ; CHECK-NEXT: renamable $d2 = COPY killed renamable $d525 ; CHECK-NEXT: renamable $d3 = COPY killed renamable $d426 ; CHECK-NEXT: tBX_RET 14 /* CC::al */, $noreg, implicit killed renamable $d7, implicit killed $q0_q127 %0:dpr_vfp2 = COPY $d428 %1:dpr_vfp2 = COPY $d229 %2:dpr_vfp2 = COPY $d730 undef %4.dsub_0:dquad = COPY %031 %4.dsub_1:dquad = COPY %132 %4.dsub_2:dquad = COPY %033 %4.dsub_3:dquad = COPY %134 tBX_RET 14, $noreg, implicit %4.dsub_3, implicit %235...36 37 38# tBX_RET uses the same vreg twice, make sure regallocfast is able to allocate a39# physical register for it and replace both references.40---41name: same_vreg_twice42tracksRegLiveness: true43body: |44 bb.0:45 liveins: $d2, $d446 47 ; CHECK-LABEL: name: same_vreg_twice48 ; CHECK: liveins: $d2, $d449 ; CHECK-NEXT: {{ $}}50 ; CHECK-NEXT: renamable $d5 = COPY killed $d451 ; CHECK-NEXT: renamable $d4 = COPY killed $d252 ; CHECK-NEXT: undef renamable $d0 = COPY renamable $d5, implicit-def $q0_q153 ; CHECK-NEXT: renamable $d1 = COPY renamable $d454 ; CHECK-NEXT: renamable $d2 = COPY killed renamable $d555 ; CHECK-NEXT: renamable $d3 = COPY killed renamable $d456 ; CHECK-NEXT: tBX_RET 14 /* CC::al */, $noreg, implicit renamable $d3, implicit killed $q0_q157 %0:dpr_vfp2 = COPY $d458 %1:dpr_vfp2 = COPY $d259 undef %4.dsub_0:dquad = COPY %060 %4.dsub_1:dquad = COPY %161 %4.dsub_2:dquad = COPY %062 %4.dsub_3:dquad = COPY %163 tBX_RET 14, $noreg, implicit %4.dsub_1, implicit %4.dsub_364...65 66# tBL partially defines two vregs, which turn out to be dead. Make sure67# regallocfast allocates a phys reg for both %0 and %1.68---69name: partial_dead70tracksRegLiveness: true71body: |72 bb.0:73 74 ; CHECK-LABEL: name: partial_dead75 ; CHECK: tBL 14 /* CC::al */, $noreg, 0, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit-def $sp, implicit-def dead $q0_q1, implicit-def dead $q2_q376 ; CHECK-NEXT: tBX_RET 14 /* CC::al */, $noreg77 tBL 14, $noreg, 0, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit-def $sp, implicit-def undef %0.dsub_0:dquad, implicit-def undef %1.dsub_2:dquad78 tBX_RET 14, $noreg79...80