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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc %s -start-before register-coalescer -mtriple=arm-apple-ios -stop-after machine-scheduler -o - -enable-subreg-liveness -verify-machineinstrs | FileCheck %s3 4# Check that when we merge live-ranges that imply offseting5# the definition of a subregister by some other subreg index,6# we take that new index into account while updating the subrange.7#8# For this specific test case, the coalescer is going to get rid9# of `%5.dsub_1:dtriple = COPY %4.dsub_3` by aligning10# %5.dsub_1:<3 x s64> with %4.dsub_3:<4 x s64>.11# This is done by moving to a bigger register class <5 x s64>12# and offseting %5 definitions with a new subregidx:13# NewVar: <5 x s64> dsub_0 dsub_1 dsub_2 dsub_3 dsub_414# %4: <4 x s64> dsub_0 dsub_1 dsub_2 dsub_315# %5: <3 x s64> <==offset===> dsub_0 dsub_1 dsub_216#17# In other %5.dsub_0 needs to be mapped to NewVar.dsub_2, %5.dsub_118# to NewVar.dsub_3 and so on. So essentially we are offseting %5 by19# dsub_2.20#21# When updating the live-ranges, the register coalescer actually22# has not rewritten the original code, so we need to fake the23# rewrite to do that update.24# This used to be wrong and this test was failling with a machine25# verifier error: No live segment at def.26#27# The test case runs through the coalescer *and* the scheduler, just28# to force the live intervals to be carried around so that the verifier29# gets a chance to verify those. If we were to just run the coalescer,30# the live intervals would be dropped before running the verifier since31# no other pass would need that analysis around.32#33# Note: The test case looks slightly more complicated than just the34# offseting part. That's because the bug needs three things to35# trigger:36# 1. Overlapping subreg lanes: here, dsub0 == <ssub0, ssub1>37# 2. Tuple registers with a possibility to coalesce the subreg index:38# here, what we explain with %5.dsub_1 == %4.dsub_339# 3. Subreg liveness enabled.40# #1 is required to trigger the splitting of subranges that implies41# looking at the IR to decide what is alive and what is not.42# #2 is what produces the IR to be out-of-synce with what the reg coalescer43# maintains for the live-ranges information.44# #3 is, well, the problem has to do with subranges updates!45#46# In the end, the expected result is to have all the variables47# being coalesced in one big (qqqq) variable.48---49name: main50alignment: 151tracksRegLiveness: true52frameInfo:53 maxAlignment: 154machineFunctionInfo: {}55body: |56 bb.0:57 liveins: $d2, $s1, $d458 59 60 ; CHECK-LABEL: name: main61 ; CHECK: liveins: $d2, $s1, $d462 ; CHECK: undef %4.dsub_0:qqqqpr_with_ssub_4 = COPY $d463 ; CHECK: %4.ssub_4:qqqqpr_with_ssub_4 = COPY $s164 ; CHECK: %4.dsub_1:qqqqpr_with_ssub_4 = COPY $d265 ; CHECK: %4.dsub_3:qqqqpr_with_ssub_4 = COPY %4.dsub_166 ; CHECK: KILL implicit-def %4.dsub_2, implicit %4.qqsub_067 ; CHECK: %4.dsub_4:qqqqpr_with_ssub_4 = COPY %4.dsub_168 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit %4.ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_969 %3:dpr_vfp2 = COPY $d470 undef %0.ssub_0:dpr_vfp2 = COPY $s171 %1:dpr_vfp2 = COPY $d272 undef %4.dsub_0:dquad = COPY %373 %4.dsub_1:dquad = COPY %174 %4.dsub_2:dquad = COPY %075 %4.dsub_3:dquad = COPY %176 KILL implicit-def undef %5.dsub_0:dtriple, implicit %477 %5.dsub_1:dtriple = COPY %4.dsub_378 %5.dsub_2:dtriple = COPY %179 tBX_RET 14, $noreg, implicit %580 81...82