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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=arm-eabi -mattr=+v6 %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-ARM3; RUN: llc -mtriple=thumbv6m-none-eabi %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-V64; RUN: llc -mtriple=thumbv7m-none-eabi %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-V75 6define i32 @test1(i32 %X) nounwind {7; CHECK-LABEL: test1:8; CHECK: @ %bb.0:9; CHECK-NEXT: rev16 r0, r010; CHECK-NEXT: bx lr11 %tmp1 = lshr i32 %X, 812 %X15 = bitcast i32 %X to i3213 %tmp4 = shl i32 %X15, 814 %tmp2 = and i32 %tmp1, 1671168015 %tmp5 = and i32 %tmp4, -1677721616 %tmp9 = and i32 %tmp1, 25517 %tmp13 = and i32 %tmp4, 6528018 %tmp6 = or i32 %tmp5, %tmp219 %tmp10 = or i32 %tmp6, %tmp1320 %tmp14 = or i32 %tmp10, %tmp921 ret i32 %tmp1422}23 24define i32 @test2(i32 %X) nounwind {25; CHECK-LABEL: test2:26; CHECK: @ %bb.0:27; CHECK-NEXT: revsh r0, r028; CHECK-NEXT: bx lr29 %tmp1 = lshr i32 %X, 830 %tmp1.upgrd.1 = trunc i32 %tmp1 to i1631 %tmp3 = trunc i32 %X to i1632 %tmp2 = and i16 %tmp1.upgrd.1, 25533 %tmp4 = shl i16 %tmp3, 834 %tmp5 = or i16 %tmp2, %tmp435 %tmp5.upgrd.2 = sext i16 %tmp5 to i3236 ret i32 %tmp5.upgrd.237}38 39; rdar://914763740define i32 @test3(i16 zeroext %a) nounwind {41; CHECK-LABEL: test3:42; CHECK: @ %bb.0: @ %entry43; CHECK-NEXT: revsh r0, r044; CHECK-NEXT: bx lr45entry:46 %0 = tail call i16 @llvm.bswap.i16(i16 %a)47 %1 = sext i16 %0 to i3248 ret i32 %149}50 51declare i16 @llvm.bswap.i16(i16) nounwind readnone52 53define i32 @test4(i16 zeroext %a) nounwind {54; CHECK-LABEL: test4:55; CHECK: @ %bb.0: @ %entry56; CHECK-NEXT: revsh r0, r057; CHECK-NEXT: bx lr58entry:59 %conv = zext i16 %a to i3260 %shr9 = lshr i16 %a, 861 %conv2 = zext i16 %shr9 to i3262 %shl = shl nuw nsw i32 %conv, 863 %or = or i32 %conv2, %shl64 %sext = shl i32 %or, 1665 %conv8 = ashr exact i32 %sext, 1666 ret i32 %conv867}68 69; rdar://960905970define i32 @test5(i32 %i) nounwind readnone {71; CHECK-ARM-LABEL: test5:72; CHECK-ARM: @ %bb.0: @ %entry73; CHECK-ARM-NEXT: revsh r0, r074; CHECK-ARM-NEXT: bx lr75;76; CHECK-V6-LABEL: test5:77; CHECK-V6: @ %bb.0: @ %entry78; CHECK-V6-NEXT: lsrs r1, r0, #879; CHECK-V6-NEXT: uxtb r1, r180; CHECK-V6-NEXT: lsls r0, r0, #2481; CHECK-V6-NEXT: asrs r0, r0, #1682; CHECK-V6-NEXT: adds r0, r0, r183; CHECK-V6-NEXT: bx lr84;85; CHECK-V7-LABEL: test5:86; CHECK-V7: @ %bb.0: @ %entry87; CHECK-V7-NEXT: revsh r0, r088; CHECK-V7-NEXT: bx lr89entry:90 %shl = shl i32 %i, 2491 %shr = ashr exact i32 %shl, 1692 %shr23 = lshr i32 %i, 893 %and = and i32 %shr23, 25594 %or = or i32 %shr, %and95 ret i32 %or96}97 98; rdar://960910899define i32 @test6(i32 %x) nounwind readnone {100; CHECK-LABEL: test6:101; CHECK: @ %bb.0: @ %entry102; CHECK-NEXT: rev16 r0, r0103; CHECK-NEXT: bx lr104entry:105 %and = shl i32 %x, 8106 %shl = and i32 %and, 65280107 %and2 = lshr i32 %x, 8108 %shr11 = and i32 %and2, 255109 %shr5 = and i32 %and2, 16711680110 %shl9 = and i32 %and, -16777216111 %or = or i32 %shr5, %shl9112 %or6 = or i32 %or, %shr11113 %or10 = or i32 %or6, %shl114 ret i32 %or10115}116 117; rdar://9164521118define i32 @test7(i32 %a) nounwind readnone {119; CHECK-ARM-LABEL: test7:120; CHECK-ARM: @ %bb.0: @ %entry121; CHECK-ARM-NEXT: rev r0, r0122; CHECK-ARM-NEXT: lsr r0, r0, #16123; CHECK-ARM-NEXT: bx lr124;125; CHECK-V6-LABEL: test7:126; CHECK-V6: @ %bb.0: @ %entry127; CHECK-V6-NEXT: rev r0, r0128; CHECK-V6-NEXT: lsrs r0, r0, #16129; CHECK-V6-NEXT: bx lr130;131; CHECK-V7-LABEL: test7:132; CHECK-V7: @ %bb.0: @ %entry133; CHECK-V7-NEXT: rev r0, r0134; CHECK-V7-NEXT: lsrs r0, r0, #16135; CHECK-V7-NEXT: bx lr136entry:137 %and = lshr i32 %a, 8138 %shr3 = and i32 %and, 255139 %and2 = shl i32 %a, 8140 %shl = and i32 %and2, 65280141 %or = or i32 %shr3, %shl142 ret i32 %or143}144 145define i32 @test8(i32 %a) nounwind readnone {146; CHECK-LABEL: test8:147; CHECK: @ %bb.0: @ %entry148; CHECK-NEXT: revsh r0, r0149; CHECK-NEXT: bx lr150entry:151 %and = lshr i32 %a, 8152 %shr4 = and i32 %and, 255153 %and2 = shl i32 %a, 8154 %or = or i32 %shr4, %and2155 %sext = shl i32 %or, 16156 %conv3 = ashr exact i32 %sext, 16157 ret i32 %conv3158}159 160; rdar://10750814161define zeroext i16 @test9(i16 zeroext %v) nounwind readnone {162; CHECK-LABEL: test9:163; CHECK: @ %bb.0: @ %entry164; CHECK-NEXT: rev16 r0, r0165; CHECK-NEXT: bx lr166entry:167 %conv = zext i16 %v to i32168 %shr4 = lshr i32 %conv, 8169 %shl = shl nuw nsw i32 %conv, 8170 %or = or i32 %shr4, %shl171 %conv3 = trunc i32 %or to i16172 ret i16 %conv3173}174 175define zeroext i16 @test10(i16 zeroext %v) nounwind readnone {176; CHECK-LABEL: test10:177; CHECK: @ %bb.0: @ %entry178; CHECK-NEXT: rev16 r0, r0179; CHECK-NEXT: bx lr180entry:181 %conv3 = call i16 @llvm.bswap.i16(i16 %v)182 ret i16 %conv3183}184 185define i32 @pr55484(i32 %0) {186; CHECK-ARM-LABEL: pr55484:187; CHECK-ARM: @ %bb.0:188; CHECK-ARM-NEXT: lsr r1, r0, #8189; CHECK-ARM-NEXT: orr r0, r1, r0, lsl #8190; CHECK-ARM-NEXT: sxth r0, r0191; CHECK-ARM-NEXT: bx lr192;193; CHECK-V6-LABEL: pr55484:194; CHECK-V6: @ %bb.0:195; CHECK-V6-NEXT: lsls r1, r0, #8196; CHECK-V6-NEXT: lsrs r0, r0, #8197; CHECK-V6-NEXT: orrs r0, r1198; CHECK-V6-NEXT: sxth r0, r0199; CHECK-V6-NEXT: bx lr200;201; CHECK-V7-LABEL: pr55484:202; CHECK-V7: @ %bb.0:203; CHECK-V7-NEXT: lsrs r1, r0, #8204; CHECK-V7-NEXT: orr.w r0, r1, r0, lsl #8205; CHECK-V7-NEXT: sxth r0, r0206; CHECK-V7-NEXT: bx lr207 %2 = lshr i32 %0, 8208 %3 = shl i32 %0, 8209 %4 = or i32 %2, %3210 %5 = trunc i32 %4 to i16211 %6 = sext i16 %5 to i32212 ret i32 %6213}214