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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=arm-eabi -mattr=+v6 %s -o - | FileCheck %s3 4 5target triple = "nvptx64-nvidia-cuda"6 7define i32 @test_simple_rotl(i32 %x) {8; CHECK-LABEL: test_simple_rotl:9; CHECK: @ %bb.0:10; CHECK-NEXT: ror r0, r0, #2511; CHECK-NEXT: bx lr12 %shl = shl i32 %x, 713 %shr = lshr i32 %x, 2514 %add = add i32 %shl, %shr15 ret i32 %add16}17 18define i32 @test_simple_rotr(i32 %x) {19; CHECK-LABEL: test_simple_rotr:20; CHECK: @ %bb.0:21; CHECK-NEXT: ror r0, r0, #722; CHECK-NEXT: bx lr23 %shr = lshr i32 %x, 724 %shl = shl i32 %x, 2525 %add = add i32 %shr, %shl26 ret i32 %add27}28 29define i32 @test_rotl_var(i32 %x, i32 %y) {30; CHECK-LABEL: test_rotl_var:31; CHECK: @ %bb.0:32; CHECK-NEXT: rsb r1, r1, #3233; CHECK-NEXT: ror r0, r0, r134; CHECK-NEXT: bx lr35 %shl = shl i32 %x, %y36 %sub = sub i32 32, %y37 %shr = lshr i32 %x, %sub38 %add = add i32 %shl, %shr39 ret i32 %add40}41 42define i32 @test_rotr_var(i32 %x, i32 %y) {43; CHECK-LABEL: test_rotr_var:44; CHECK: @ %bb.0:45; CHECK-NEXT: ror r0, r0, r146; CHECK-NEXT: bx lr47 %shr = lshr i32 %x, %y48 %sub = sub i32 32, %y49 %shl = shl i32 %x, %sub50 %add = add i32 %shr, %shl51 ret i32 %add52}53 54define i32 @test_invalid_rotl_var_and(i32 %x, i32 %y) {55; CHECK-LABEL: test_invalid_rotl_var_and:56; CHECK: @ %bb.0:57; CHECK-NEXT: rsb r2, r1, #058; CHECK-NEXT: and r2, r2, #3159; CHECK-NEXT: lsr r2, r0, r260; CHECK-NEXT: add r0, r2, r0, lsl r161; CHECK-NEXT: bx lr62 %shr = shl i32 %x, %y63 %sub = sub nsw i32 0, %y64 %and = and i32 %sub, 3165 %shl = lshr i32 %x, %and66 %add = add i32 %shl, %shr67 ret i32 %add68}69 70define i32 @test_invalid_rotr_var_and(i32 %x, i32 %y) {71; CHECK-LABEL: test_invalid_rotr_var_and:72; CHECK: @ %bb.0:73; CHECK-NEXT: lsr r2, r0, r174; CHECK-NEXT: rsb r1, r1, #075; CHECK-NEXT: and r1, r1, #3176; CHECK-NEXT: add r0, r2, r0, lsl r177; CHECK-NEXT: bx lr78 %shr = lshr i32 %x, %y79 %sub = sub nsw i32 0, %y80 %and = and i32 %sub, 3181 %shl = shl i32 %x, %and82 %add = add i32 %shr, %shl83 ret i32 %add84}85 86define i32 @test_fshl_special_case(i32 %x0, i32 %x1, i32 %y) {87; CHECK-LABEL: test_fshl_special_case:88; CHECK: @ %bb.0:89; CHECK-NEXT: lsl r0, r0, r290; CHECK-NEXT: eor r2, r2, #3191; CHECK-NEXT: lsr r1, r1, #192; CHECK-NEXT: add r0, r0, r1, lsr r293; CHECK-NEXT: bx lr94 %shl = shl i32 %x0, %y95 %srli = lshr i32 %x1, 196 %x = xor i32 %y, 3197 %srlo = lshr i32 %srli, %x98 %o = add i32 %shl, %srlo99 ret i32 %o100}101 102define i32 @test_fshr_special_case(i32 %x0, i32 %x1, i32 %y) {103; CHECK-LABEL: test_fshr_special_case:104; CHECK: @ %bb.0:105; CHECK-NEXT: lsr r1, r1, r2106; CHECK-NEXT: eor r2, r2, #31107; CHECK-NEXT: lsl r0, r0, #1108; CHECK-NEXT: add r0, r1, r0, lsl r2109; CHECK-NEXT: bx lr110 %shl = lshr i32 %x1, %y111 %srli = shl i32 %x0, 1112 %x = xor i32 %y, 31113 %srlo = shl i32 %srli, %x114 %o = add i32 %shl, %srlo115 ret i32 %o116}117 118define i64 @test_rotl_udiv_special_case(i64 %i) {119; CHECK-LABEL: test_rotl_udiv_special_case:120; CHECK: @ %bb.0:121; CHECK-NEXT: .save {r11, lr}122; CHECK-NEXT: push {r11, lr}123; CHECK-NEXT: adds r2, r0, r1124; CHECK-NEXT: ldr r12, .LCPI8_0125; CHECK-NEXT: adc lr, r2, #0126; CHECK-NEXT: umull r3, r2, lr, r12127; CHECK-NEXT: bic r3, r2, #1128; CHECK-NEXT: add r2, r3, r2, lsr #1129; CHECK-NEXT: ldr r3, .LCPI8_1130; CHECK-NEXT: sub r2, lr, r2131; CHECK-NEXT: subs r0, r0, r2132; CHECK-NEXT: sbc r1, r1, #0133; CHECK-NEXT: umull r2, lr, r0, r12134; CHECK-NEXT: mla r0, r0, r3, lr135; CHECK-NEXT: mla r0, r1, r12, r0136; CHECK-NEXT: lsl r1, r2, #28137; CHECK-NEXT: orr r1, r1, r0, lsr #4138; CHECK-NEXT: lsl r0, r0, #28139; CHECK-NEXT: orr r0, r0, r2, lsr #4140; CHECK-NEXT: pop {r11, pc}141; CHECK-NEXT: .p2align 2142; CHECK-NEXT: @ %bb.1:143; CHECK-NEXT: .LCPI8_0:144; CHECK-NEXT: .long 2863311531 @ 0xaaaaaaab145; CHECK-NEXT: .LCPI8_1:146; CHECK-NEXT: .long 2863311530 @ 0xaaaaaaaa147 %lhs_div = udiv i64 %i, 3148 %rhs_div = udiv i64 %i, 48149 %lhs_shift = shl i64 %lhs_div, 60150 %out = add i64 %lhs_shift, %rhs_div151 ret i64 %out152}153 154define i32 @test_rotl_mul_special_case(i32 %i) {155; CHECK-LABEL: test_rotl_mul_special_case:156; CHECK: @ %bb.0:157; CHECK-NEXT: add r0, r0, r0, lsl #3158; CHECK-NEXT: ror r0, r0, #25159; CHECK-NEXT: bx lr160 %lhs_mul = mul i32 %i, 9161 %rhs_mul = mul i32 %i, 1152162 %lhs_shift = lshr i32 %lhs_mul, 25163 %out = add i32 %lhs_shift, %rhs_mul164 ret i32 %out165}166 167define i64 @test_rotl_mul_with_mask_special_case(i64 %i) {168; CHECK-LABEL: test_rotl_mul_with_mask_special_case:169; CHECK: @ %bb.0:170; CHECK-NEXT: mov r2, #9171; CHECK-NEXT: add r1, r1, r1, lsl #3172; CHECK-NEXT: umull r2, r3, r0, r2173; CHECK-NEXT: and r0, r0, #1174; CHECK-NEXT: lsl r0, r0, #7175; CHECK-NEXT: add r1, r3, r1176; CHECK-NEXT: orr r0, r0, r1, lsr #25177; CHECK-NEXT: mov r1, #0178; CHECK-NEXT: bx lr179 %lhs_mul = mul i64 %i, 1152180 %rhs_mul = mul i64 %i, 9181 %lhs_and = and i64 %lhs_mul, 160182 %rhs_shift = lshr i64 %rhs_mul, 57183 %out = add i64 %lhs_and, %rhs_shift184 ret i64 %out185}186 187define i32 @test_fshl_with_mask_special_case(i32 %x) {188; CHECK-LABEL: test_fshl_with_mask_special_case:189; CHECK: @ %bb.0:190; CHECK-NEXT: mov r1, #32191; CHECK-NEXT: orr r0, r1, r0, ror #27192; CHECK-NEXT: bic r0, r0, #30193; CHECK-NEXT: bx lr194 %or1 = or i32 %x, 1195 %sh1 = shl i32 %or1, 5196 %sh2 = lshr i32 %x, 27197 %1 = and i32 %sh2, 1198 %r = add i32 %sh1, %1199 ret i32 %r200}201