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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=thumbv6m-none-eabi | FileCheck %s --check-prefix=CHECK-T13; RUN: llc < %s -mtriple=thumbv7m-none-eabi | FileCheck %s --check-prefix=CHECK-T2 --check-prefix=CHECK-T2NODSP4; RUN: llc < %s -mtriple=thumbv7em-none-eabi | FileCheck %s --check-prefix=CHECK-T2 --check-prefix=CHECK-T2DSP5; RUN: llc < %s -mtriple=armv8a-none-eabi | FileCheck %s --check-prefix=CHECK-ARM6 7declare i4 @llvm.sadd.sat.i4(i4, i4)8declare i8 @llvm.sadd.sat.i8(i8, i8)9declare i16 @llvm.sadd.sat.i16(i16, i16)10declare i32 @llvm.sadd.sat.i32(i32, i32)11declare i64 @llvm.sadd.sat.i64(i64, i64)12 13define i32 @func32(i32 %x, i32 %y, i32 %z) nounwind {14; CHECK-T1-LABEL: func32:15; CHECK-T1: @ %bb.0:16; CHECK-T1-NEXT: muls r1, r2, r117; CHECK-T1-NEXT: adds r0, r0, r118; CHECK-T1-NEXT: bvc .LBB0_219; CHECK-T1-NEXT: @ %bb.1:20; CHECK-T1-NEXT: asrs r1, r0, #3121; CHECK-T1-NEXT: movs r0, #122; CHECK-T1-NEXT: lsls r0, r0, #3123; CHECK-T1-NEXT: eors r0, r124; CHECK-T1-NEXT: .LBB0_2:25; CHECK-T1-NEXT: bx lr26;27; CHECK-T2NODSP-LABEL: func32:28; CHECK-T2NODSP: @ %bb.0:29; CHECK-T2NODSP-NEXT: mla r1, r1, r2, r030; CHECK-T2NODSP-NEXT: mov.w r2, #-214748364831; CHECK-T2NODSP-NEXT: cmp r1, r032; CHECK-T2NODSP-NEXT: it vs33; CHECK-T2NODSP-NEXT: eorvs.w r1, r2, r1, asr #3134; CHECK-T2NODSP-NEXT: mov r0, r135; CHECK-T2NODSP-NEXT: bx lr36;37; CHECK-T2DSP-LABEL: func32:38; CHECK-T2DSP: @ %bb.0:39; CHECK-T2DSP-NEXT: muls r1, r2, r140; CHECK-T2DSP-NEXT: qadd r0, r0, r141; CHECK-T2DSP-NEXT: bx lr42;43; CHECK-ARM-LABEL: func32:44; CHECK-ARM: @ %bb.0:45; CHECK-ARM-NEXT: mul r1, r1, r246; CHECK-ARM-NEXT: qadd r0, r0, r147; CHECK-ARM-NEXT: bx lr48 %a = mul i32 %y, %z49 %tmp = call i32 @llvm.sadd.sat.i32(i32 %x, i32 %a)50 ret i32 %tmp51}52 53define i64 @func64(i64 %x, i64 %y, i64 %z) nounwind {54; CHECK-T1-LABEL: func64:55; CHECK-T1: @ %bb.0:56; CHECK-T1-NEXT: .save {r4, lr}57; CHECK-T1-NEXT: push {r4, lr}58; CHECK-T1-NEXT: ldr r3, [sp, #12]59; CHECK-T1-NEXT: mov r2, r160; CHECK-T1-NEXT: eors r2, r361; CHECK-T1-NEXT: ldr r4, [sp, #8]62; CHECK-T1-NEXT: adds r4, r0, r463; CHECK-T1-NEXT: adcs r3, r164; CHECK-T1-NEXT: eors r1, r365; CHECK-T1-NEXT: bics r1, r266; CHECK-T1-NEXT: asrs r0, r3, #3167; CHECK-T1-NEXT: movs r2, #168; CHECK-T1-NEXT: lsls r2, r2, #3169; CHECK-T1-NEXT: eors r2, r070; CHECK-T1-NEXT: cmp r1, #071; CHECK-T1-NEXT: bpl .LBB1_372; CHECK-T1-NEXT: @ %bb.1:73; CHECK-T1-NEXT: bpl .LBB1_474; CHECK-T1-NEXT: .LBB1_2:75; CHECK-T1-NEXT: mov r1, r276; CHECK-T1-NEXT: pop {r4, pc}77; CHECK-T1-NEXT: .LBB1_3:78; CHECK-T1-NEXT: mov r0, r479; CHECK-T1-NEXT: bmi .LBB1_280; CHECK-T1-NEXT: .LBB1_4:81; CHECK-T1-NEXT: mov r2, r382; CHECK-T1-NEXT: mov r1, r283; CHECK-T1-NEXT: pop {r4, pc}84;85; CHECK-T2-LABEL: func64:86; CHECK-T2: @ %bb.0:87; CHECK-T2-NEXT: ldr r2, [sp]88; CHECK-T2-NEXT: ldr.w r12, [sp, #4]89; CHECK-T2-NEXT: adds r0, r0, r290; CHECK-T2-NEXT: adc.w r2, r1, r1291; CHECK-T2-NEXT: eor.w r3, r1, r1292; CHECK-T2-NEXT: eors r1, r293; CHECK-T2-NEXT: bics r1, r394; CHECK-T2-NEXT: it mi95; CHECK-T2-NEXT: asrmi r0, r2, #3196; CHECK-T2-NEXT: mov.w r1, #-214748364897; CHECK-T2-NEXT: it mi98; CHECK-T2-NEXT: eormi.w r2, r1, r2, asr #3199; CHECK-T2-NEXT: mov r1, r2100; CHECK-T2-NEXT: bx lr101;102; CHECK-ARM-LABEL: func64:103; CHECK-ARM: @ %bb.0:104; CHECK-ARM-NEXT: ldr r12, [sp]105; CHECK-ARM-NEXT: ldr r2, [sp, #4]106; CHECK-ARM-NEXT: adds r0, r0, r12107; CHECK-ARM-NEXT: eor r3, r1, r2108; CHECK-ARM-NEXT: adc r2, r1, r2109; CHECK-ARM-NEXT: eor r1, r1, r2110; CHECK-ARM-NEXT: bics r1, r1, r3111; CHECK-ARM-NEXT: asrmi r0, r2, #31112; CHECK-ARM-NEXT: mov r1, #-2147483648113; CHECK-ARM-NEXT: eormi r2, r1, r2, asr #31114; CHECK-ARM-NEXT: mov r1, r2115; CHECK-ARM-NEXT: bx lr116 %a = mul i64 %y, %z117 %tmp = call i64 @llvm.sadd.sat.i64(i64 %x, i64 %z)118 ret i64 %tmp119}120 121define signext i16 @func16(i16 signext %x, i16 signext %y, i16 signext %z) nounwind {122; CHECK-T1-LABEL: func16:123; CHECK-T1: @ %bb.0:124; CHECK-T1-NEXT: muls r1, r2, r1125; CHECK-T1-NEXT: sxth r1, r1126; CHECK-T1-NEXT: adds r0, r0, r1127; CHECK-T1-NEXT: ldr r1, .LCPI2_0128; CHECK-T1-NEXT: cmp r0, r1129; CHECK-T1-NEXT: blt .LBB2_2130; CHECK-T1-NEXT: @ %bb.1:131; CHECK-T1-NEXT: mov r0, r1132; CHECK-T1-NEXT: .LBB2_2:133; CHECK-T1-NEXT: ldr r1, .LCPI2_1134; CHECK-T1-NEXT: cmp r0, r1135; CHECK-T1-NEXT: bgt .LBB2_4136; CHECK-T1-NEXT: @ %bb.3:137; CHECK-T1-NEXT: mov r0, r1138; CHECK-T1-NEXT: .LBB2_4:139; CHECK-T1-NEXT: bx lr140; CHECK-T1-NEXT: .p2align 2141; CHECK-T1-NEXT: @ %bb.5:142; CHECK-T1-NEXT: .LCPI2_0:143; CHECK-T1-NEXT: .long 32767 @ 0x7fff144; CHECK-T1-NEXT: .LCPI2_1:145; CHECK-T1-NEXT: .long 4294934528 @ 0xffff8000146;147; CHECK-T2NODSP-LABEL: func16:148; CHECK-T2NODSP: @ %bb.0:149; CHECK-T2NODSP-NEXT: muls r1, r2, r1150; CHECK-T2NODSP-NEXT: sxth r1, r1151; CHECK-T2NODSP-NEXT: add r0, r1152; CHECK-T2NODSP-NEXT: ssat r0, #16, r0153; CHECK-T2NODSP-NEXT: bx lr154;155; CHECK-T2DSP-LABEL: func16:156; CHECK-T2DSP: @ %bb.0:157; CHECK-T2DSP-NEXT: muls r1, r2, r1158; CHECK-T2DSP-NEXT: qadd16 r0, r0, r1159; CHECK-T2DSP-NEXT: sxth r0, r0160; CHECK-T2DSP-NEXT: bx lr161;162; CHECK-ARM-LABEL: func16:163; CHECK-ARM: @ %bb.0:164; CHECK-ARM-NEXT: smulbb r1, r1, r2165; CHECK-ARM-NEXT: qadd16 r0, r0, r1166; CHECK-ARM-NEXT: sxth r0, r0167; CHECK-ARM-NEXT: bx lr168 %a = mul i16 %y, %z169 %tmp = call i16 @llvm.sadd.sat.i16(i16 %x, i16 %a)170 ret i16 %tmp171}172 173define signext i8 @func8(i8 signext %x, i8 signext %y, i8 signext %z) nounwind {174; CHECK-T1-LABEL: func8:175; CHECK-T1: @ %bb.0:176; CHECK-T1-NEXT: muls r1, r2, r1177; CHECK-T1-NEXT: sxtb r1, r1178; CHECK-T1-NEXT: adds r0, r0, r1179; CHECK-T1-NEXT: movs r1, #127180; CHECK-T1-NEXT: cmp r0, #127181; CHECK-T1-NEXT: blt .LBB3_2182; CHECK-T1-NEXT: @ %bb.1:183; CHECK-T1-NEXT: mov r0, r1184; CHECK-T1-NEXT: .LBB3_2:185; CHECK-T1-NEXT: mvns r1, r1186; CHECK-T1-NEXT: cmp r0, r1187; CHECK-T1-NEXT: bgt .LBB3_4188; CHECK-T1-NEXT: @ %bb.3:189; CHECK-T1-NEXT: mov r0, r1190; CHECK-T1-NEXT: .LBB3_4:191; CHECK-T1-NEXT: bx lr192;193; CHECK-T2NODSP-LABEL: func8:194; CHECK-T2NODSP: @ %bb.0:195; CHECK-T2NODSP-NEXT: muls r1, r2, r1196; CHECK-T2NODSP-NEXT: sxtb r1, r1197; CHECK-T2NODSP-NEXT: add r0, r1198; CHECK-T2NODSP-NEXT: ssat r0, #8, r0199; CHECK-T2NODSP-NEXT: bx lr200;201; CHECK-T2DSP-LABEL: func8:202; CHECK-T2DSP: @ %bb.0:203; CHECK-T2DSP-NEXT: muls r1, r2, r1204; CHECK-T2DSP-NEXT: qadd8 r0, r0, r1205; CHECK-T2DSP-NEXT: sxtb r0, r0206; CHECK-T2DSP-NEXT: bx lr207;208; CHECK-ARM-LABEL: func8:209; CHECK-ARM: @ %bb.0:210; CHECK-ARM-NEXT: smulbb r1, r1, r2211; CHECK-ARM-NEXT: qadd8 r0, r0, r1212; CHECK-ARM-NEXT: sxtb r0, r0213; CHECK-ARM-NEXT: bx lr214 %a = mul i8 %y, %z215 %tmp = call i8 @llvm.sadd.sat.i8(i8 %x, i8 %a)216 ret i8 %tmp217}218 219define signext i4 @func4(i4 signext %x, i4 signext %y, i4 signext %z) nounwind {220; CHECK-T1-LABEL: func4:221; CHECK-T1: @ %bb.0:222; CHECK-T1-NEXT: muls r1, r2, r1223; CHECK-T1-NEXT: lsls r1, r1, #28224; CHECK-T1-NEXT: asrs r1, r1, #28225; CHECK-T1-NEXT: adds r0, r0, r1226; CHECK-T1-NEXT: movs r1, #7227; CHECK-T1-NEXT: cmp r0, #7228; CHECK-T1-NEXT: blt .LBB4_2229; CHECK-T1-NEXT: @ %bb.1:230; CHECK-T1-NEXT: mov r0, r1231; CHECK-T1-NEXT: .LBB4_2:232; CHECK-T1-NEXT: mvns r1, r1233; CHECK-T1-NEXT: cmp r0, r1234; CHECK-T1-NEXT: bgt .LBB4_4235; CHECK-T1-NEXT: @ %bb.3:236; CHECK-T1-NEXT: mov r0, r1237; CHECK-T1-NEXT: .LBB4_4:238; CHECK-T1-NEXT: bx lr239;240; CHECK-T2NODSP-LABEL: func4:241; CHECK-T2NODSP: @ %bb.0:242; CHECK-T2NODSP-NEXT: muls r1, r2, r1243; CHECK-T2NODSP-NEXT: lsls r1, r1, #28244; CHECK-T2NODSP-NEXT: add.w r0, r0, r1, asr #28245; CHECK-T2NODSP-NEXT: ssat r0, #4, r0246; CHECK-T2NODSP-NEXT: bx lr247;248; CHECK-T2DSP-LABEL: func4:249; CHECK-T2DSP: @ %bb.0:250; CHECK-T2DSP-NEXT: muls r1, r2, r1251; CHECK-T2DSP-NEXT: lsls r0, r0, #28252; CHECK-T2DSP-NEXT: lsls r1, r1, #28253; CHECK-T2DSP-NEXT: qadd r0, r0, r1254; CHECK-T2DSP-NEXT: asrs r0, r0, #28255; CHECK-T2DSP-NEXT: bx lr256;257; CHECK-ARM-LABEL: func4:258; CHECK-ARM: @ %bb.0:259; CHECK-ARM-NEXT: smulbb r1, r1, r2260; CHECK-ARM-NEXT: lsl r0, r0, #28261; CHECK-ARM-NEXT: lsl r1, r1, #28262; CHECK-ARM-NEXT: qadd r0, r0, r1263; CHECK-ARM-NEXT: asr r0, r0, #28264; CHECK-ARM-NEXT: bx lr265 %a = mul i4 %y, %z266 %tmp = call i4 @llvm.sadd.sat.i4(i4 %x, i4 %a)267 ret i4 %tmp268}269