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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc -mtriple=armv7-unknown-eabi %s -o - | FileCheck %s3 4define i8 @scmp_8_8(i8 signext %x, i8 signext %y) nounwind {5; CHECK-LABEL: scmp_8_8:6; CHECK: @ %bb.0:7; CHECK-NEXT: subs r0, r0, r18; CHECK-NEXT: movwgt r0, #19; CHECK-NEXT: mvnlt r0, #010; CHECK-NEXT: bx lr11 %1 = call i8 @llvm.scmp(i8 %x, i8 %y)12 ret i8 %113}14 15define i8 @scmp_8_16(i16 signext %x, i16 signext %y) nounwind {16; CHECK-LABEL: scmp_8_16:17; CHECK: @ %bb.0:18; CHECK-NEXT: subs r0, r0, r119; CHECK-NEXT: movwgt r0, #120; CHECK-NEXT: mvnlt r0, #021; CHECK-NEXT: bx lr22 %1 = call i8 @llvm.scmp(i16 %x, i16 %y)23 ret i8 %124}25 26define i8 @scmp_8_32(i32 %x, i32 %y) nounwind {27; CHECK-LABEL: scmp_8_32:28; CHECK: @ %bb.0:29; CHECK-NEXT: subs r0, r0, r130; CHECK-NEXT: movwgt r0, #131; CHECK-NEXT: mvnlt r0, #032; CHECK-NEXT: bx lr33 %1 = call i8 @llvm.scmp(i32 %x, i32 %y)34 ret i8 %135}36 37define i8 @scmp_8_64(i64 %x, i64 %y) nounwind {38; CHECK-LABEL: scmp_8_64:39; CHECK: @ %bb.0:40; CHECK-NEXT: .save {r11, lr}41; CHECK-NEXT: push {r11, lr}42; CHECK-NEXT: subs lr, r0, r243; CHECK-NEXT: mov r12, #044; CHECK-NEXT: sbcs lr, r1, r345; CHECK-NEXT: mov lr, #046; CHECK-NEXT: movwlt lr, #147; CHECK-NEXT: subs r0, r2, r048; CHECK-NEXT: sbcs r0, r3, r149; CHECK-NEXT: movwlt r12, #150; CHECK-NEXT: sub r0, r12, lr51; CHECK-NEXT: pop {r11, pc}52 %1 = call i8 @llvm.scmp(i64 %x, i64 %y)53 ret i8 %154}55 56define i8 @scmp_8_128(i128 %x, i128 %y) nounwind {57; CHECK-LABEL: scmp_8_128:58; CHECK: @ %bb.0:59; CHECK-NEXT: .save {r4, r5, r6, r7, r11, lr}60; CHECK-NEXT: push {r4, r5, r6, r7, r11, lr}61; CHECK-NEXT: ldr r4, [sp, #24]62; CHECK-NEXT: mov r5, #063; CHECK-NEXT: ldr r6, [sp, #28]64; CHECK-NEXT: subs r7, r0, r465; CHECK-NEXT: ldr r12, [sp, #32]66; CHECK-NEXT: sbcs r7, r1, r667; CHECK-NEXT: ldr lr, [sp, #36]68; CHECK-NEXT: sbcs r7, r2, r1269; CHECK-NEXT: sbcs r7, r3, lr70; CHECK-NEXT: mov r7, #071; CHECK-NEXT: movwlt r7, #172; CHECK-NEXT: subs r0, r4, r073; CHECK-NEXT: sbcs r0, r6, r174; CHECK-NEXT: sbcs r0, r12, r275; CHECK-NEXT: sbcs r0, lr, r376; CHECK-NEXT: movwlt r5, #177; CHECK-NEXT: sub r0, r5, r778; CHECK-NEXT: pop {r4, r5, r6, r7, r11, pc}79 %1 = call i8 @llvm.scmp(i128 %x, i128 %y)80 ret i8 %181}82 83define i32 @scmp_32_32(i32 %x, i32 %y) nounwind {84; CHECK-LABEL: scmp_32_32:85; CHECK: @ %bb.0:86; CHECK-NEXT: subs r0, r0, r187; CHECK-NEXT: movwgt r0, #188; CHECK-NEXT: mvnlt r0, #089; CHECK-NEXT: bx lr90 %1 = call i32 @llvm.scmp(i32 %x, i32 %y)91 ret i32 %192}93 94define i32 @scmp_neg(i32 %x, i32 %y) nounwind {95; CHECK-LABEL: scmp_neg:96; CHECK: @ %bb.0:97; CHECK-NEXT: adds r0, r0, r198; CHECK-NEXT: movwgt r0, #199; CHECK-NEXT: mvnlt r0, #0100; CHECK-NEXT: bx lr101 %yy = sub nsw i32 0, %y102 %1 = call i32 @llvm.scmp(i32 %x, i32 %yy)103 ret i32 %1104}105 106define i32 @scmp_32_64(i64 %x, i64 %y) nounwind {107; CHECK-LABEL: scmp_32_64:108; CHECK: @ %bb.0:109; CHECK-NEXT: .save {r11, lr}110; CHECK-NEXT: push {r11, lr}111; CHECK-NEXT: subs lr, r0, r2112; CHECK-NEXT: mov r12, #0113; CHECK-NEXT: sbcs lr, r1, r3114; CHECK-NEXT: mov lr, #0115; CHECK-NEXT: movwlt lr, #1116; CHECK-NEXT: subs r0, r2, r0117; CHECK-NEXT: sbcs r0, r3, r1118; CHECK-NEXT: movwlt r12, #1119; CHECK-NEXT: sub r0, r12, lr120; CHECK-NEXT: pop {r11, pc}121 %1 = call i32 @llvm.scmp(i64 %x, i64 %y)122 ret i32 %1123}124 125define i64 @scmp_64_64(i64 %x, i64 %y) nounwind {126; CHECK-LABEL: scmp_64_64:127; CHECK: @ %bb.0:128; CHECK-NEXT: .save {r11, lr}129; CHECK-NEXT: push {r11, lr}130; CHECK-NEXT: subs lr, r0, r2131; CHECK-NEXT: mov r12, #0132; CHECK-NEXT: sbcs lr, r1, r3133; CHECK-NEXT: mov lr, #0134; CHECK-NEXT: movwlt lr, #1135; CHECK-NEXT: subs r0, r2, r0136; CHECK-NEXT: sbcs r0, r3, r1137; CHECK-NEXT: movwlt r12, #1138; CHECK-NEXT: sub r0, r12, lr139; CHECK-NEXT: asr r1, r0, #31140; CHECK-NEXT: pop {r11, pc}141 %1 = call i64 @llvm.scmp(i64 %x, i64 %y)142 ret i64 %1143}144