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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=arm-eabi-unknown-unknown | FileCheck %s --check-prefix=ARM3; RUN: llc < %s -mtriple=thumbv6t2-eabi-unknown-unknown | FileCheck %s --check-prefix=THUMB24; RUN: llc < %s -mtriple=thumb-eabi-unknown-unknown | FileCheck %s --check-prefix=THUMB5 6; Select of constants: control flow / conditional moves can always be replaced by logic+math (but may not be worth it?).7; Test the zeroext/signext variants of each pattern to see if that makes a difference.8 9; select Cond, 0, 1 --> zext (!Cond)10 11define i32 @select_0_or_1(i1 %cond) {12; ARM-LABEL: select_0_or_1:13; ARM: @ %bb.0:14; ARM-NEXT: mov r1, #115; ARM-NEXT: bic r0, r1, r016; ARM-NEXT: mov pc, lr17;18; THUMB2-LABEL: select_0_or_1:19; THUMB2: @ %bb.0:20; THUMB2-NEXT: movs r1, #121; THUMB2-NEXT: bic.w r0, r1, r022; THUMB2-NEXT: bx lr23;24; THUMB-LABEL: select_0_or_1:25; THUMB: @ %bb.0:26; THUMB-NEXT: movs r1, #127; THUMB-NEXT: bics r1, r028; THUMB-NEXT: movs r0, r129; THUMB-NEXT: bx lr30 %sel = select i1 %cond, i32 0, i32 131 ret i32 %sel32}33 34define i32 @select_0_or_1_zeroext(i1 zeroext %cond) {35; ARM-LABEL: select_0_or_1_zeroext:36; ARM: @ %bb.0:37; ARM-NEXT: eor r0, r0, #138; ARM-NEXT: mov pc, lr39;40; THUMB2-LABEL: select_0_or_1_zeroext:41; THUMB2: @ %bb.0:42; THUMB2-NEXT: eor r0, r0, #143; THUMB2-NEXT: bx lr44;45; THUMB-LABEL: select_0_or_1_zeroext:46; THUMB: @ %bb.0:47; THUMB-NEXT: movs r1, #148; THUMB-NEXT: eors r0, r149; THUMB-NEXT: bx lr50 %sel = select i1 %cond, i32 0, i32 151 ret i32 %sel52}53 54define i32 @select_0_or_1_signext(i1 signext %cond) {55; ARM-LABEL: select_0_or_1_signext:56; ARM: @ %bb.0:57; ARM-NEXT: mov r1, #158; ARM-NEXT: bic r0, r1, r059; ARM-NEXT: mov pc, lr60;61; THUMB2-LABEL: select_0_or_1_signext:62; THUMB2: @ %bb.0:63; THUMB2-NEXT: movs r1, #164; THUMB2-NEXT: bic.w r0, r1, r065; THUMB2-NEXT: bx lr66;67; THUMB-LABEL: select_0_or_1_signext:68; THUMB: @ %bb.0:69; THUMB-NEXT: movs r1, #170; THUMB-NEXT: bics r1, r071; THUMB-NEXT: movs r0, r172; THUMB-NEXT: bx lr73 %sel = select i1 %cond, i32 0, i32 174 ret i32 %sel75}76 77; select Cond, 1, 0 --> zext (Cond)78 79define i32 @select_1_or_0(i1 %cond) {80; ARM-LABEL: select_1_or_0:81; ARM: @ %bb.0:82; ARM-NEXT: and r0, r0, #183; ARM-NEXT: mov pc, lr84;85; THUMB2-LABEL: select_1_or_0:86; THUMB2: @ %bb.0:87; THUMB2-NEXT: and r0, r0, #188; THUMB2-NEXT: bx lr89;90; THUMB-LABEL: select_1_or_0:91; THUMB: @ %bb.0:92; THUMB-NEXT: movs r1, #193; THUMB-NEXT: ands r0, r194; THUMB-NEXT: bx lr95 %sel = select i1 %cond, i32 1, i32 096 ret i32 %sel97}98 99define i32 @select_1_or_0_zeroext(i1 zeroext %cond) {100; ARM-LABEL: select_1_or_0_zeroext:101; ARM: @ %bb.0:102; ARM-NEXT: mov pc, lr103;104; THUMB2-LABEL: select_1_or_0_zeroext:105; THUMB2: @ %bb.0:106; THUMB2-NEXT: bx lr107;108; THUMB-LABEL: select_1_or_0_zeroext:109; THUMB: @ %bb.0:110; THUMB-NEXT: bx lr111 %sel = select i1 %cond, i32 1, i32 0112 ret i32 %sel113}114 115define i32 @select_1_or_0_signext(i1 signext %cond) {116; ARM-LABEL: select_1_or_0_signext:117; ARM: @ %bb.0:118; ARM-NEXT: and r0, r0, #1119; ARM-NEXT: mov pc, lr120;121; THUMB2-LABEL: select_1_or_0_signext:122; THUMB2: @ %bb.0:123; THUMB2-NEXT: and r0, r0, #1124; THUMB2-NEXT: bx lr125;126; THUMB-LABEL: select_1_or_0_signext:127; THUMB: @ %bb.0:128; THUMB-NEXT: movs r1, #1129; THUMB-NEXT: ands r0, r1130; THUMB-NEXT: bx lr131 %sel = select i1 %cond, i32 1, i32 0132 ret i32 %sel133}134 135; select Cond, 0, -1 --> sext (!Cond)136 137define i32 @select_0_or_neg1(i1 %cond) {138; ARM-LABEL: select_0_or_neg1:139; ARM: @ %bb.0:140; ARM-NEXT: and r0, r0, #1141; ARM-NEXT: sub r0, r0, #1142; ARM-NEXT: mov pc, lr143;144; THUMB2-LABEL: select_0_or_neg1:145; THUMB2: @ %bb.0:146; THUMB2-NEXT: and r0, r0, #1147; THUMB2-NEXT: subs r0, #1148; THUMB2-NEXT: bx lr149;150; THUMB-LABEL: select_0_or_neg1:151; THUMB: @ %bb.0:152; THUMB-NEXT: movs r1, #1153; THUMB-NEXT: ands r1, r0154; THUMB-NEXT: subs r0, r1, #1155; THUMB-NEXT: bx lr156 %sel = select i1 %cond, i32 0, i32 -1157 ret i32 %sel158}159 160define i32 @select_0_or_neg1_zeroext(i1 zeroext %cond) {161; ARM-LABEL: select_0_or_neg1_zeroext:162; ARM: @ %bb.0:163; ARM-NEXT: sub r0, r0, #1164; ARM-NEXT: mov pc, lr165;166; THUMB2-LABEL: select_0_or_neg1_zeroext:167; THUMB2: @ %bb.0:168; THUMB2-NEXT: subs r0, #1169; THUMB2-NEXT: bx lr170;171; THUMB-LABEL: select_0_or_neg1_zeroext:172; THUMB: @ %bb.0:173; THUMB-NEXT: subs r0, r0, #1174; THUMB-NEXT: bx lr175 %sel = select i1 %cond, i32 0, i32 -1176 ret i32 %sel177}178 179define i32 @select_0_or_neg1_signext(i1 signext %cond) {180; ARM-LABEL: select_0_or_neg1_signext:181; ARM: @ %bb.0:182; ARM-NEXT: mvn r0, r0183; ARM-NEXT: mov pc, lr184;185; THUMB2-LABEL: select_0_or_neg1_signext:186; THUMB2: @ %bb.0:187; THUMB2-NEXT: mvns r0, r0188; THUMB2-NEXT: bx lr189;190; THUMB-LABEL: select_0_or_neg1_signext:191; THUMB: @ %bb.0:192; THUMB-NEXT: mvns r0, r0193; THUMB-NEXT: bx lr194 %sel = select i1 %cond, i32 0, i32 -1195 ret i32 %sel196}197 198define i32 @select_0_or_neg1_alt(i1 %cond) {199; ARM-LABEL: select_0_or_neg1_alt:200; ARM: @ %bb.0:201; ARM-NEXT: and r0, r0, #1202; ARM-NEXT: sub r0, r0, #1203; ARM-NEXT: mov pc, lr204;205; THUMB2-LABEL: select_0_or_neg1_alt:206; THUMB2: @ %bb.0:207; THUMB2-NEXT: and r0, r0, #1208; THUMB2-NEXT: subs r0, #1209; THUMB2-NEXT: bx lr210;211; THUMB-LABEL: select_0_or_neg1_alt:212; THUMB: @ %bb.0:213; THUMB-NEXT: movs r1, #1214; THUMB-NEXT: ands r1, r0215; THUMB-NEXT: subs r0, r1, #1216; THUMB-NEXT: bx lr217 %z = zext i1 %cond to i32218 %add = add i32 %z, -1219 ret i32 %add220}221 222define i32 @select_0_or_neg1_alt_zeroext(i1 zeroext %cond) {223; ARM-LABEL: select_0_or_neg1_alt_zeroext:224; ARM: @ %bb.0:225; ARM-NEXT: sub r0, r0, #1226; ARM-NEXT: mov pc, lr227;228; THUMB2-LABEL: select_0_or_neg1_alt_zeroext:229; THUMB2: @ %bb.0:230; THUMB2-NEXT: subs r0, #1231; THUMB2-NEXT: bx lr232;233; THUMB-LABEL: select_0_or_neg1_alt_zeroext:234; THUMB: @ %bb.0:235; THUMB-NEXT: subs r0, r0, #1236; THUMB-NEXT: bx lr237 %z = zext i1 %cond to i32238 %add = add i32 %z, -1239 ret i32 %add240}241 242define i32 @select_0_or_neg1_alt_signext(i1 signext %cond) {243; ARM-LABEL: select_0_or_neg1_alt_signext:244; ARM: @ %bb.0:245; ARM-NEXT: mvn r0, r0246; ARM-NEXT: mov pc, lr247;248; THUMB2-LABEL: select_0_or_neg1_alt_signext:249; THUMB2: @ %bb.0:250; THUMB2-NEXT: mvns r0, r0251; THUMB2-NEXT: bx lr252;253; THUMB-LABEL: select_0_or_neg1_alt_signext:254; THUMB: @ %bb.0:255; THUMB-NEXT: mvns r0, r0256; THUMB-NEXT: bx lr257 %z = zext i1 %cond to i32258 %add = add i32 %z, -1259 ret i32 %add260}261 262; select Cond, -1, 0 --> sext (Cond)263 264define i32 @select_neg1_or_0(i1 %cond) {265; ARM-LABEL: select_neg1_or_0:266; ARM: @ %bb.0:267; ARM-NEXT: and r0, r0, #1268; ARM-NEXT: rsb r0, r0, #0269; ARM-NEXT: mov pc, lr270;271; THUMB2-LABEL: select_neg1_or_0:272; THUMB2: @ %bb.0:273; THUMB2-NEXT: and r0, r0, #1274; THUMB2-NEXT: rsbs r0, r0, #0275; THUMB2-NEXT: bx lr276;277; THUMB-LABEL: select_neg1_or_0:278; THUMB: @ %bb.0:279; THUMB-NEXT: movs r1, #1280; THUMB-NEXT: ands r1, r0281; THUMB-NEXT: rsbs r0, r1, #0282; THUMB-NEXT: bx lr283 %sel = select i1 %cond, i32 -1, i32 0284 ret i32 %sel285}286 287define i32 @select_neg1_or_0_zeroext(i1 zeroext %cond) {288; ARM-LABEL: select_neg1_or_0_zeroext:289; ARM: @ %bb.0:290; ARM-NEXT: rsb r0, r0, #0291; ARM-NEXT: mov pc, lr292;293; THUMB2-LABEL: select_neg1_or_0_zeroext:294; THUMB2: @ %bb.0:295; THUMB2-NEXT: rsbs r0, r0, #0296; THUMB2-NEXT: bx lr297;298; THUMB-LABEL: select_neg1_or_0_zeroext:299; THUMB: @ %bb.0:300; THUMB-NEXT: rsbs r0, r0, #0301; THUMB-NEXT: bx lr302 %sel = select i1 %cond, i32 -1, i32 0303 ret i32 %sel304}305 306define i32 @select_neg1_or_0_signext(i1 signext %cond) {307; ARM-LABEL: select_neg1_or_0_signext:308; ARM: @ %bb.0:309; ARM-NEXT: mov pc, lr310;311; THUMB2-LABEL: select_neg1_or_0_signext:312; THUMB2: @ %bb.0:313; THUMB2-NEXT: bx lr314;315; THUMB-LABEL: select_neg1_or_0_signext:316; THUMB: @ %bb.0:317; THUMB-NEXT: bx lr318 %sel = select i1 %cond, i32 -1, i32 0319 ret i32 %sel320}321 322; select Cond, C+1, C --> add (zext Cond), C323 324define i32 @select_Cplus1_C(i1 %cond) {325; ARM-LABEL: select_Cplus1_C:326; ARM: @ %bb.0:327; ARM-NEXT: mov r1, #41328; ARM-NEXT: tst r0, #1329; ARM-NEXT: movne r1, #42330; ARM-NEXT: mov r0, r1331; ARM-NEXT: mov pc, lr332;333; THUMB2-LABEL: select_Cplus1_C:334; THUMB2: @ %bb.0:335; THUMB2-NEXT: lsls r0, r0, #31336; THUMB2-NEXT: mov.w r0, #41337; THUMB2-NEXT: it ne338; THUMB2-NEXT: movne r0, #42339; THUMB2-NEXT: bx lr340;341; THUMB-LABEL: select_Cplus1_C:342; THUMB: @ %bb.0:343; THUMB-NEXT: lsls r0, r0, #31344; THUMB-NEXT: bne .LBB15_2345; THUMB-NEXT: @ %bb.1:346; THUMB-NEXT: movs r0, #41347; THUMB-NEXT: bx lr348; THUMB-NEXT: .LBB15_2:349; THUMB-NEXT: movs r0, #42350; THUMB-NEXT: bx lr351 %sel = select i1 %cond, i32 42, i32 41352 ret i32 %sel353}354 355define i32 @select_Cplus1_C_zeroext(i1 zeroext %cond) {356; ARM-LABEL: select_Cplus1_C_zeroext:357; ARM: @ %bb.0:358; ARM-NEXT: mov r1, #41359; ARM-NEXT: cmp r0, #0360; ARM-NEXT: movne r1, #42361; ARM-NEXT: mov r0, r1362; ARM-NEXT: mov pc, lr363;364; THUMB2-LABEL: select_Cplus1_C_zeroext:365; THUMB2: @ %bb.0:366; THUMB2-NEXT: movs r1, #41367; THUMB2-NEXT: cmp r0, #0368; THUMB2-NEXT: it ne369; THUMB2-NEXT: movne r1, #42370; THUMB2-NEXT: mov r0, r1371; THUMB2-NEXT: bx lr372;373; THUMB-LABEL: select_Cplus1_C_zeroext:374; THUMB: @ %bb.0:375; THUMB-NEXT: cmp r0, #0376; THUMB-NEXT: bne .LBB16_2377; THUMB-NEXT: @ %bb.1:378; THUMB-NEXT: movs r0, #41379; THUMB-NEXT: bx lr380; THUMB-NEXT: .LBB16_2:381; THUMB-NEXT: movs r0, #42382; THUMB-NEXT: bx lr383 %sel = select i1 %cond, i32 42, i32 41384 ret i32 %sel385}386 387define i32 @select_Cplus1_C_signext(i1 signext %cond) {388; ARM-LABEL: select_Cplus1_C_signext:389; ARM: @ %bb.0:390; ARM-NEXT: mov r1, #41391; ARM-NEXT: tst r0, #1392; ARM-NEXT: movne r1, #42393; ARM-NEXT: mov r0, r1394; ARM-NEXT: mov pc, lr395;396; THUMB2-LABEL: select_Cplus1_C_signext:397; THUMB2: @ %bb.0:398; THUMB2-NEXT: lsls r0, r0, #31399; THUMB2-NEXT: mov.w r0, #41400; THUMB2-NEXT: it ne401; THUMB2-NEXT: movne r0, #42402; THUMB2-NEXT: bx lr403;404; THUMB-LABEL: select_Cplus1_C_signext:405; THUMB: @ %bb.0:406; THUMB-NEXT: lsls r0, r0, #31407; THUMB-NEXT: bne .LBB17_2408; THUMB-NEXT: @ %bb.1:409; THUMB-NEXT: movs r0, #41410; THUMB-NEXT: bx lr411; THUMB-NEXT: .LBB17_2:412; THUMB-NEXT: movs r0, #42413; THUMB-NEXT: bx lr414 %sel = select i1 %cond, i32 42, i32 41415 ret i32 %sel416}417 418; select Cond, C, C+1 --> add (sext Cond), C419 420define i32 @select_C_Cplus1(i1 %cond) {421; ARM-LABEL: select_C_Cplus1:422; ARM: @ %bb.0:423; ARM-NEXT: mov r1, #42424; ARM-NEXT: tst r0, #1425; ARM-NEXT: movne r1, #41426; ARM-NEXT: mov r0, r1427; ARM-NEXT: mov pc, lr428;429; THUMB2-LABEL: select_C_Cplus1:430; THUMB2: @ %bb.0:431; THUMB2-NEXT: lsls r0, r0, #31432; THUMB2-NEXT: mov.w r0, #42433; THUMB2-NEXT: it ne434; THUMB2-NEXT: movne r0, #41435; THUMB2-NEXT: bx lr436;437; THUMB-LABEL: select_C_Cplus1:438; THUMB: @ %bb.0:439; THUMB-NEXT: lsls r0, r0, #31440; THUMB-NEXT: bne .LBB18_2441; THUMB-NEXT: @ %bb.1:442; THUMB-NEXT: movs r0, #42443; THUMB-NEXT: bx lr444; THUMB-NEXT: .LBB18_2:445; THUMB-NEXT: movs r0, #41446; THUMB-NEXT: bx lr447 %sel = select i1 %cond, i32 41, i32 42448 ret i32 %sel449}450 451define i32 @select_C_Cplus1_zeroext(i1 zeroext %cond) {452; ARM-LABEL: select_C_Cplus1_zeroext:453; ARM: @ %bb.0:454; ARM-NEXT: mov r1, #42455; ARM-NEXT: cmp r0, #0456; ARM-NEXT: movne r1, #41457; ARM-NEXT: mov r0, r1458; ARM-NEXT: mov pc, lr459;460; THUMB2-LABEL: select_C_Cplus1_zeroext:461; THUMB2: @ %bb.0:462; THUMB2-NEXT: movs r1, #42463; THUMB2-NEXT: cmp r0, #0464; THUMB2-NEXT: it ne465; THUMB2-NEXT: movne r1, #41466; THUMB2-NEXT: mov r0, r1467; THUMB2-NEXT: bx lr468;469; THUMB-LABEL: select_C_Cplus1_zeroext:470; THUMB: @ %bb.0:471; THUMB-NEXT: cmp r0, #0472; THUMB-NEXT: bne .LBB19_2473; THUMB-NEXT: @ %bb.1:474; THUMB-NEXT: movs r0, #42475; THUMB-NEXT: bx lr476; THUMB-NEXT: .LBB19_2:477; THUMB-NEXT: movs r0, #41478; THUMB-NEXT: bx lr479 %sel = select i1 %cond, i32 41, i32 42480 ret i32 %sel481}482 483define i32 @select_C_Cplus1_signext(i1 signext %cond) {484; ARM-LABEL: select_C_Cplus1_signext:485; ARM: @ %bb.0:486; ARM-NEXT: mov r1, #42487; ARM-NEXT: tst r0, #1488; ARM-NEXT: movne r1, #41489; ARM-NEXT: mov r0, r1490; ARM-NEXT: mov pc, lr491;492; THUMB2-LABEL: select_C_Cplus1_signext:493; THUMB2: @ %bb.0:494; THUMB2-NEXT: lsls r0, r0, #31495; THUMB2-NEXT: mov.w r0, #42496; THUMB2-NEXT: it ne497; THUMB2-NEXT: movne r0, #41498; THUMB2-NEXT: bx lr499;500; THUMB-LABEL: select_C_Cplus1_signext:501; THUMB: @ %bb.0:502; THUMB-NEXT: lsls r0, r0, #31503; THUMB-NEXT: bne .LBB20_2504; THUMB-NEXT: @ %bb.1:505; THUMB-NEXT: movs r0, #42506; THUMB-NEXT: bx lr507; THUMB-NEXT: .LBB20_2:508; THUMB-NEXT: movs r0, #41509; THUMB-NEXT: bx lr510 %sel = select i1 %cond, i32 41, i32 42511 ret i32 %sel512}513 514; In general, select of 2 constants could be:515; select Cond, C1, C2 --> add (mul (zext Cond), C1-C2), C2 --> add (and (sext Cond), C1-C2), C2516 517define i32 @select_C1_C2(i1 %cond) {518; ARM-LABEL: select_C1_C2:519; ARM: @ %bb.0:520; ARM-NEXT: mov r1, #165521; ARM-NEXT: tst r0, #1522; ARM-NEXT: orr r1, r1, #256523; ARM-NEXT: moveq r1, #42524; ARM-NEXT: mov r0, r1525; ARM-NEXT: mov pc, lr526;527; THUMB2-LABEL: select_C1_C2:528; THUMB2: @ %bb.0:529; THUMB2-NEXT: lsls r0, r0, #31530; THUMB2-NEXT: mov.w r0, #42531; THUMB2-NEXT: it ne532; THUMB2-NEXT: movwne r0, #421533; THUMB2-NEXT: bx lr534;535; THUMB-LABEL: select_C1_C2:536; THUMB: @ %bb.0:537; THUMB-NEXT: lsls r0, r0, #31538; THUMB-NEXT: bne .LBB21_2539; THUMB-NEXT: @ %bb.1:540; THUMB-NEXT: movs r0, #42541; THUMB-NEXT: bx lr542; THUMB-NEXT: .LBB21_2:543; THUMB-NEXT: movs r0, #255544; THUMB-NEXT: adds r0, #166545; THUMB-NEXT: bx lr546 %sel = select i1 %cond, i32 421, i32 42547 ret i32 %sel548}549 550define i32 @select_C1_C2_zeroext(i1 zeroext %cond) {551; ARM-LABEL: select_C1_C2_zeroext:552; ARM: @ %bb.0:553; ARM-NEXT: mov r1, #165554; ARM-NEXT: cmp r0, #0555; ARM-NEXT: orr r1, r1, #256556; ARM-NEXT: moveq r1, #42557; ARM-NEXT: mov r0, r1558; ARM-NEXT: mov pc, lr559;560; THUMB2-LABEL: select_C1_C2_zeroext:561; THUMB2: @ %bb.0:562; THUMB2-NEXT: movs r1, #42563; THUMB2-NEXT: cmp r0, #0564; THUMB2-NEXT: it ne565; THUMB2-NEXT: movwne r1, #421566; THUMB2-NEXT: mov r0, r1567; THUMB2-NEXT: bx lr568;569; THUMB-LABEL: select_C1_C2_zeroext:570; THUMB: @ %bb.0:571; THUMB-NEXT: cmp r0, #0572; THUMB-NEXT: bne .LBB22_2573; THUMB-NEXT: @ %bb.1:574; THUMB-NEXT: movs r0, #42575; THUMB-NEXT: bx lr576; THUMB-NEXT: .LBB22_2:577; THUMB-NEXT: movs r0, #255578; THUMB-NEXT: adds r0, #166579; THUMB-NEXT: bx lr580 %sel = select i1 %cond, i32 421, i32 42581 ret i32 %sel582}583 584define i32 @select_C1_C2_signext(i1 signext %cond) {585; ARM-LABEL: select_C1_C2_signext:586; ARM: @ %bb.0:587; ARM-NEXT: mov r1, #165588; ARM-NEXT: tst r0, #1589; ARM-NEXT: orr r1, r1, #256590; ARM-NEXT: moveq r1, #42591; ARM-NEXT: mov r0, r1592; ARM-NEXT: mov pc, lr593;594; THUMB2-LABEL: select_C1_C2_signext:595; THUMB2: @ %bb.0:596; THUMB2-NEXT: lsls r0, r0, #31597; THUMB2-NEXT: mov.w r0, #42598; THUMB2-NEXT: it ne599; THUMB2-NEXT: movwne r0, #421600; THUMB2-NEXT: bx lr601;602; THUMB-LABEL: select_C1_C2_signext:603; THUMB: @ %bb.0:604; THUMB-NEXT: lsls r0, r0, #31605; THUMB-NEXT: bne .LBB23_2606; THUMB-NEXT: @ %bb.1:607; THUMB-NEXT: movs r0, #42608; THUMB-NEXT: bx lr609; THUMB-NEXT: .LBB23_2:610; THUMB-NEXT: movs r0, #255611; THUMB-NEXT: adds r0, #166612; THUMB-NEXT: bx lr613 %sel = select i1 %cond, i32 421, i32 42614 ret i32 %sel615}616 617; 4295032833 = 0x100010001.618; This becomes an opaque constant via ConstantHoisting, so we don't fold it into the select.619 620define i64 @opaque_constant1(i1 %cond, i64 %x) {621; ARM-LABEL: opaque_constant1:622; ARM: @ %bb.0:623; ARM-NEXT: .save {r4, lr}624; ARM-NEXT: push {r4, lr}625; ARM-NEXT: mov lr, #1626; ARM-NEXT: ands r12, r0, #1627; ARM-NEXT: mov r0, #23628; ARM-NEXT: orr lr, lr, #65536629; ARM-NEXT: mvnne r0, #3630; ARM-NEXT: and r4, r0, lr631; ARM-NEXT: movne r12, #1632; ARM-NEXT: subs r0, r4, #1633; ARM-NEXT: eor r2, r2, lr634; ARM-NEXT: eor r3, r3, #1635; ARM-NEXT: sbc r1, r12, #0636; ARM-NEXT: orrs r2, r2, r3637; ARM-NEXT: movne r0, r4638; ARM-NEXT: movne r1, r12639; ARM-NEXT: pop {r4, lr}640; ARM-NEXT: mov pc, lr641;642; THUMB2-LABEL: opaque_constant1:643; THUMB2: @ %bb.0:644; THUMB2-NEXT: .save {r7, lr}645; THUMB2-NEXT: push {r7, lr}646; THUMB2-NEXT: ands r12, r0, #1647; THUMB2-NEXT: mov.w lr, #1648; THUMB2-NEXT: it ne649; THUMB2-NEXT: movne.w r12, #1650; THUMB2-NEXT: it ne651; THUMB2-NEXT: movne.w lr, #65536652; THUMB2-NEXT: subs.w r0, lr, #1653; THUMB2-NEXT: eor r3, r3, #1654; THUMB2-NEXT: sbc r1, r12, #0655; THUMB2-NEXT: eor r2, r2, #65537656; THUMB2-NEXT: orrs r2, r3657; THUMB2-NEXT: itt ne658; THUMB2-NEXT: movne r0, lr659; THUMB2-NEXT: movne r1, r12660; THUMB2-NEXT: pop {r7, pc}661;662; THUMB-LABEL: opaque_constant1:663; THUMB: @ %bb.0:664; THUMB-NEXT: .save {r4, r5, r6, r7, lr}665; THUMB-NEXT: push {r4, r5, r6, r7, lr}666; THUMB-NEXT: movs r7, #1667; THUMB-NEXT: ands r0, r7668; THUMB-NEXT: subs r1, r0, #1669; THUMB-NEXT: mov r12, r0670; THUMB-NEXT: mov r4, r12671; THUMB-NEXT: sbcs r4, r1672; THUMB-NEXT: cmp r0, #0673; THUMB-NEXT: bne .LBB24_2674; THUMB-NEXT: @ %bb.1:675; THUMB-NEXT: movs r5, #23676; THUMB-NEXT: b .LBB24_3677; THUMB-NEXT: .LBB24_2:678; THUMB-NEXT: movs r0, #3679; THUMB-NEXT: mvns r5, r0680; THUMB-NEXT: .LBB24_3:681; THUMB-NEXT: ldr r0, .LCPI24_0682; THUMB-NEXT: ands r5, r0683; THUMB-NEXT: movs r6, #0684; THUMB-NEXT: subs r0, r5, #1685; THUMB-NEXT: mov r12, r4686; THUMB-NEXT: mov r1, r12687; THUMB-NEXT: sbcs r1, r6688; THUMB-NEXT: eors r3, r7689; THUMB-NEXT: ldr r6, .LCPI24_0690; THUMB-NEXT: eors r2, r6691; THUMB-NEXT: orrs r2, r3692; THUMB-NEXT: cmp r2, #0693; THUMB-NEXT: beq .LBB24_5694; THUMB-NEXT: @ %bb.4:695; THUMB-NEXT: mov r12, r4696; THUMB-NEXT: mov r1, r12697; THUMB-NEXT: .LBB24_5:698; THUMB-NEXT: beq .LBB24_7699; THUMB-NEXT: @ %bb.6:700; THUMB-NEXT: movs r0, r5701; THUMB-NEXT: .LBB24_7:702; THUMB-NEXT: pop {r4, r5, r6, r7}703; THUMB-NEXT: pop {r2}704; THUMB-NEXT: bx r2705; THUMB-NEXT: .p2align 2706; THUMB-NEXT: @ %bb.8:707; THUMB-NEXT: .LCPI24_0:708; THUMB-NEXT: .long 65537 @ 0x10001709 %sel = select i1 %cond, i64 -4, i64 23710 %bo = and i64 %sel, 4295032833 ; 0x100010001711 %cmp = icmp eq i64 %x, 4295032833712 %sext = sext i1 %cmp to i64713 %add = add i64 %bo, %sext714 ret i64 %add715}716 717; 65537 == 0x10001.718; This becomes an opaque constant via ConstantHoisting, so we don't fold it into the select.719 720define i64 @opaque_constant2(i1 %cond, i64 %x) {721; ARM-LABEL: opaque_constant2:722; ARM: @ %bb.0:723; ARM-NEXT: mov r1, #1724; ARM-NEXT: tst r0, #1725; ARM-NEXT: orr r1, r1, #65536726; ARM-NEXT: moveq r1, #23727; ARM-NEXT: bic r0, r1, #22728; ARM-NEXT: mov r1, #0729; ARM-NEXT: mov pc, lr730;731; THUMB2-LABEL: opaque_constant2:732; THUMB2: @ %bb.0:733; THUMB2-NEXT: lsls r0, r0, #31734; THUMB2-NEXT: mov.w r1, #0735; THUMB2-NEXT: mov.w r0, #1736; THUMB2-NEXT: it ne737; THUMB2-NEXT: movne.w r0, #65537738; THUMB2-NEXT: bx lr739;740; THUMB-LABEL: opaque_constant2:741; THUMB: @ %bb.0:742; THUMB-NEXT: lsls r0, r0, #31743; THUMB-NEXT: bne .LBB25_2744; THUMB-NEXT: @ %bb.1:745; THUMB-NEXT: movs r0, #23746; THUMB-NEXT: b .LBB25_3747; THUMB-NEXT: .LBB25_2:748; THUMB-NEXT: ldr r0, .LCPI25_0749; THUMB-NEXT: .LBB25_3:750; THUMB-NEXT: movs r1, #22751; THUMB-NEXT: bics r0, r1752; THUMB-NEXT: movs r1, #0753; THUMB-NEXT: bx lr754; THUMB-NEXT: .p2align 2755; THUMB-NEXT: @ %bb.4:756; THUMB-NEXT: .LCPI25_0:757; THUMB-NEXT: .long 65537 @ 0x10001758 %sel = select i1 %cond, i64 65537, i64 23759 %bo = and i64 %sel, 65537760 ret i64 %bo761}762 763define i64 @func(i64 %arg) {764; ARM-LABEL: func:765; ARM: @ %bb.0: @ %entry766; ARM-NEXT: adds r0, r0, #1767; ARM-NEXT: mov r2, #0768; ARM-NEXT: adcs r0, r1, #0769; ARM-NEXT: mov r1, #0770; ARM-NEXT: adcs r0, r2, #0771; ARM-NEXT: movne r0, #8772; ARM-NEXT: mov pc, lr773;774; THUMB2-LABEL: func:775; THUMB2: @ %bb.0: @ %entry776; THUMB2-NEXT: adds r0, #1777; THUMB2-NEXT: mov.w r2, #0778; THUMB2-NEXT: adcs r0, r1, #0779; THUMB2-NEXT: mov.w r1, #0780; THUMB2-NEXT: adcs r0, r2, #0781; THUMB2-NEXT: it ne782; THUMB2-NEXT: movne r0, #8783; THUMB2-NEXT: bx lr784;785; THUMB-LABEL: func:786; THUMB: @ %bb.0: @ %entry787; THUMB-NEXT: .save {r4, lr}788; THUMB-NEXT: push {r4, lr}789; THUMB-NEXT: movs r2, #0790; THUMB-NEXT: adds r3, r0, #1791; THUMB-NEXT: mov r12, r1792; THUMB-NEXT: mov r3, r12793; THUMB-NEXT: adcs r3, r2794; THUMB-NEXT: mov r12, r2795; THUMB-NEXT: mov r3, r12796; THUMB-NEXT: adcs r3, r2797; THUMB-NEXT: subs r4, r3, #1798; THUMB-NEXT: adds r0, r0, #1799; THUMB-NEXT: adcs r1, r2800; THUMB-NEXT: sbcs r3, r4801; THUMB-NEXT: lsls r0, r3, #3802; THUMB-NEXT: movs r1, r2803; THUMB-NEXT: pop {r4}804; THUMB-NEXT: pop {r2}805; THUMB-NEXT: bx r2806entry:807 %0 = add i64 %arg, 1808 %1 = icmp ult i64 %0, 1809 %2 = select i1 %1, i64 8, i64 0810 ret i64 %2811}812