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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=arm-- -mcpu=cortex-a8 | FileCheck %s -check-prefixes=CHECK,ARM3; RUN: llc < %s -mtriple=thumb-- -mcpu=cortex-a8 | FileCheck %s -check-prefixes=CHECK,T24; rdar://86628255 6define i32 @t1(i32 %a, i32 %b, i32 %c) nounwind {7; ARM-LABEL: t1:8; ARM: @ %bb.0:9; ARM-NEXT: mov r0, r110; ARM-NEXT: cmp r2, #1011; ARM-NEXT: suble r0, r0, #-214748364712; ARM-NEXT: bx lr13;14; T2-LABEL: t1:15; T2: @ %bb.0:16; T2-NEXT: mov r0, r117; T2-NEXT: mvn r1, #-214748364818; T2-NEXT: cmp r2, #1019; T2-NEXT: it le20; T2-NEXT: addle r0, r121; T2-NEXT: bx lr22 %tmp1 = icmp sgt i32 %c, 1023 %tmp2 = select i1 %tmp1, i32 0, i32 214748364724 %tmp3 = add i32 %tmp2, %b25 ret i32 %tmp326}27 28define i32 @t2(i32 %a, i32 %b, i32 %c, i32 %d) nounwind {29; ARM-LABEL: t2:30; ARM: @ %bb.0:31; ARM-NEXT: mov r0, r132; ARM-NEXT: cmp r2, #1033; ARM-NEXT: suble r0, r0, #1034; ARM-NEXT: bx lr35;36; T2-LABEL: t2:37; T2: @ %bb.0:38; T2-NEXT: mov r0, r139; T2-NEXT: cmp r2, #1040; T2-NEXT: it le41; T2-NEXT: suble r0, #1042; T2-NEXT: bx lr43 %tmp1 = icmp sgt i32 %c, 1044 %tmp2 = select i1 %tmp1, i32 0, i32 1045 %tmp3 = sub i32 %b, %tmp246 ret i32 %tmp347}48 49define i32 @t3(i32 %a, i32 %b, i32 %x, i32 %y) nounwind {50; ARM-LABEL: t3:51; ARM: @ %bb.0:52; ARM-NEXT: cmp r0, r153; ARM-NEXT: andge r3, r3, r254; ARM-NEXT: mov r0, r355; ARM-NEXT: bx lr56;57; T2-LABEL: t3:58; T2: @ %bb.0:59; T2-NEXT: cmp r0, r160; T2-NEXT: it ge61; T2-NEXT: andge r3, r262; T2-NEXT: mov r0, r363; T2-NEXT: bx lr64 %cond = icmp slt i32 %a, %b65 %z = select i1 %cond, i32 -1, i32 %x66 %s = and i32 %z, %y67 ret i32 %s68}69 70define i32 @t4(i32 %a, i32 %b, i32 %x, i32 %y) nounwind {71; ARM-LABEL: t4:72; ARM: @ %bb.0:73; ARM-NEXT: cmp r0, r174; ARM-NEXT: orrge r3, r3, r275; ARM-NEXT: mov r0, r376; ARM-NEXT: bx lr77;78; T2-LABEL: t4:79; T2: @ %bb.0:80; T2-NEXT: cmp r0, r181; T2-NEXT: it ge82; T2-NEXT: orrge r3, r283; T2-NEXT: mov r0, r384; T2-NEXT: bx lr85 %cond = icmp slt i32 %a, %b86 %z = select i1 %cond, i32 0, i32 %x87 %s = or i32 %z, %y88 ret i32 %s89}90 91define i32 @t5(i32 %a, i32 %b, i32 %c) nounwind {92; ARM-LABEL: t5:93; ARM: @ %bb.0: @ %entry94; ARM-NEXT: cmp r0, r195; ARM-NEXT: orreq r2, r2, #196; ARM-NEXT: mov r0, r297; ARM-NEXT: bx lr98;99; T2-LABEL: t5:100; T2: @ %bb.0: @ %entry101; T2-NEXT: cmp r0, r1102; T2-NEXT: it eq103; T2-NEXT: orreq r2, r2, #1104; T2-NEXT: mov r0, r2105; T2-NEXT: bx lr106entry:107 %tmp1 = icmp eq i32 %a, %b108 %tmp2 = zext i1 %tmp1 to i32109 %tmp3 = or i32 %tmp2, %c110 ret i32 %tmp3111}112 113define i32 @t6(i32 %a, i32 %b, i32 %c, i32 %d) nounwind {114; ARM-LABEL: t6:115; ARM: @ %bb.0:116; ARM-NEXT: cmp r0, r1117; ARM-NEXT: eorlt r3, r3, r2118; ARM-NEXT: mov r0, r3119; ARM-NEXT: bx lr120;121; T2-LABEL: t6:122; T2: @ %bb.0:123; T2-NEXT: cmp r0, r1124; T2-NEXT: it lt125; T2-NEXT: eorlt r3, r2126; T2-NEXT: mov r0, r3127; T2-NEXT: bx lr128 %cond = icmp slt i32 %a, %b129 %tmp1 = select i1 %cond, i32 %c, i32 0130 %tmp2 = xor i32 %tmp1, %d131 ret i32 %tmp2132}133 134define i32 @t7(i32 %a, i32 %b, i32 %c) nounwind {135; ARM-LABEL: t7:136; ARM: @ %bb.0: @ %entry137; ARM-NEXT: cmp r0, r1138; ARM-NEXT: andeq r2, r2, r2, lsl #1139; ARM-NEXT: mov r0, r2140; ARM-NEXT: bx lr141;142; T2-LABEL: t7:143; T2: @ %bb.0: @ %entry144; T2-NEXT: cmp r0, r1145; T2-NEXT: it eq146; T2-NEXT: andeq.w r2, r2, r2, lsl #1147; T2-NEXT: mov r0, r2148; T2-NEXT: bx lr149entry:150 %tmp1 = shl i32 %c, 1151 %cond = icmp eq i32 %a, %b152 %tmp2 = select i1 %cond, i32 %tmp1, i32 -1153 %tmp3 = and i32 %c, %tmp2154 ret i32 %tmp3155}156 157; Fold ORRri into movcc.158define i32 @t8(i32 %a, i32 %b) nounwind {159; ARM-LABEL: t8:160; ARM: @ %bb.0:161; ARM-NEXT: cmp r0, r1162; ARM-NEXT: orrge r0, r1, #1163; ARM-NEXT: bx lr164;165; T2-LABEL: t8:166; T2: @ %bb.0:167; T2-NEXT: cmp r0, r1168; T2-NEXT: it ge169; T2-NEXT: orrge r0, r1, #1170; T2-NEXT: bx lr171 %x = or i32 %b, 1172 %cond = icmp slt i32 %a, %b173 %tmp1 = select i1 %cond, i32 %a, i32 %x174 ret i32 %tmp1175}176 177; Fold ANDrr into movcc.178define i32 @t9(i32 %a, i32 %b, i32 %c) nounwind {179; ARM-LABEL: t9:180; ARM: @ %bb.0:181; ARM-NEXT: cmp r0, r1182; ARM-NEXT: andge r0, r1, r2183; ARM-NEXT: bx lr184;185; T2-LABEL: t9:186; T2: @ %bb.0:187; T2-NEXT: cmp r0, r1188; T2-NEXT: it ge189; T2-NEXT: andge.w r0, r1, r2190; T2-NEXT: bx lr191 %x = and i32 %b, %c192 %cond = icmp slt i32 %a, %b193 %tmp1 = select i1 %cond, i32 %a, i32 %x194 ret i32 %tmp1195}196 197; Fold EORrs into movcc.198define i32 @t10(i32 %a, i32 %b, i32 %c, i32 %d) nounwind {199; ARM-LABEL: t10:200; ARM: @ %bb.0:201; ARM-NEXT: cmp r0, r1202; ARM-NEXT: eorge r0, r1, r2, lsl #7203; ARM-NEXT: bx lr204;205; T2-LABEL: t10:206; T2: @ %bb.0:207; T2-NEXT: cmp r0, r1208; T2-NEXT: it ge209; T2-NEXT: eorge.w r0, r1, r2, lsl #7210; T2-NEXT: bx lr211 %s = shl i32 %c, 7212 %x = xor i32 %b, %s213 %cond = icmp slt i32 %a, %b214 %tmp1 = select i1 %cond, i32 %a, i32 %x215 ret i32 %tmp1216}217 218; Fold ORRri into movcc, reversing the condition.219define i32 @t11(i32 %a, i32 %b) nounwind {220; ARM-LABEL: t11:221; ARM: @ %bb.0:222; ARM-NEXT: cmp r0, r1223; ARM-NEXT: orrlt r0, r1, #1224; ARM-NEXT: bx lr225;226; T2-LABEL: t11:227; T2: @ %bb.0:228; T2-NEXT: cmp r0, r1229; T2-NEXT: it lt230; T2-NEXT: orrlt r0, r1, #1231; T2-NEXT: bx lr232 %x = or i32 %b, 1233 %cond = icmp slt i32 %a, %b234 %tmp1 = select i1 %cond, i32 %x, i32 %a235 ret i32 %tmp1236}237 238; Fold ADDri12 into movcc239define i32 @t12(i32 %a, i32 %b) nounwind {240; ARM-LABEL: t12:241; ARM: @ %bb.0:242; ARM-NEXT: cmp r0, r1243; ARM-NEXT: movw r2, #3000244; ARM-NEXT: addge r0, r1, r2245; ARM-NEXT: bx lr246;247; T2-LABEL: t12:248; T2: @ %bb.0:249; T2-NEXT: cmp r0, r1250; T2-NEXT: it ge251; T2-NEXT: addwge r0, r1, #3000252; T2-NEXT: bx lr253 %x = add i32 %b, 3000254 %cond = icmp slt i32 %a, %b255 %tmp1 = select i1 %cond, i32 %a, i32 %x256 ret i32 %tmp1257}258 259; Handle frame index operands.260define void @pr13628() nounwind uwtable align 2 {261; ARM-LABEL: pr13628:262; ARM: @ %bb.0:263; ARM-NEXT: push {r11, lr}264; ARM-NEXT: sub sp, sp, #256265; ARM-NEXT: ldrb r1, [r0]266; ARM-NEXT: mov r0, sp267; ARM-NEXT: cmp r1, #0268; ARM-NEXT: moveq r0, r1269; ARM-NEXT: bl bar270; ARM-NEXT: add sp, sp, #256271; ARM-NEXT: pop {r11, pc}272;273; T2-LABEL: pr13628:274; T2: @ %bb.0:275; T2-NEXT: push {r7, lr}276; T2-NEXT: sub sp, #256277; T2-NEXT: ldrb r1, [r0]278; T2-NEXT: mov r0, sp279; T2-NEXT: cmp r1, #0280; T2-NEXT: it eq281; T2-NEXT: moveq r0, r1282; T2-NEXT: bl bar283; T2-NEXT: add sp, #256284; T2-NEXT: pop {r7, pc}285 %x3 = alloca i8, i32 256, align 8286 %x4 = load i8, ptr undef, align 1287 %x5 = icmp ne i8 %x4, 0288 %x6 = select i1 %x5, ptr %x3, ptr null289 call void @bar(ptr %x6) nounwind290 ret void291}292declare void @bar(ptr)293 294; Fold zext i1 into predicated add295define i32 @t13(i32 %c, i32 %a) nounwind readnone ssp {296; ARM-LABEL: t13:297; ARM: @ %bb.0: @ %entry298; ARM-NEXT: cmp r1, #10299; ARM-NEXT: addgt r0, r0, #1300; ARM-NEXT: bx lr301;302; T2-LABEL: t13:303; T2: @ %bb.0: @ %entry304; T2-NEXT: cmp r1, #10305; T2-NEXT: it gt306; T2-NEXT: addgt r0, #1307; T2-NEXT: bx lr308entry:309 %cmp = icmp sgt i32 %a, 10310 %conv = zext i1 %cmp to i32311 %add = add i32 %conv, %c312 ret i32 %add313}314 315; Fold sext i1 into predicated sub316define i32 @t14(i32 %c, i32 %a) nounwind readnone ssp {317; ARM-LABEL: t14:318; ARM: @ %bb.0: @ %entry319; ARM-NEXT: cmp r1, #10320; ARM-NEXT: subgt r0, r0, #1321; ARM-NEXT: bx lr322;323; T2-LABEL: t14:324; T2: @ %bb.0: @ %entry325; T2-NEXT: cmp r1, #10326; T2-NEXT: it gt327; T2-NEXT: subgt r0, #1328; T2-NEXT: bx lr329entry:330 %cmp = icmp sgt i32 %a, 10331 %conv = sext i1 %cmp to i32332 %add = add i32 %conv, %c333 ret i32 %add334}335 336; Fold the xor into the select.337define i32 @t15(i32 %p) {338; ARM-LABEL: t15:339; ARM: @ %bb.0: @ %entry340; ARM-NEXT: mov r1, #3341; ARM-NEXT: cmp r0, #8342; ARM-NEXT: movwgt r1, #0343; ARM-NEXT: mov r0, r1344; ARM-NEXT: bx lr345;346; T2-LABEL: t15:347; T2: @ %bb.0: @ %entry348; T2-NEXT: movs r1, #3349; T2-NEXT: cmp r0, #8350; T2-NEXT: it gt351; T2-NEXT: movgt r1, #0352; T2-NEXT: mov r0, r1353; T2-NEXT: bx lr354entry:355 %cmp = icmp sgt i32 %p, 8356 %a = select i1 %cmp, i32 1, i32 2357 %xor = xor i32 %a, 1358 ret i32 %xor359}360 361define i32 @t16(i32 %x, i32 %y) {362; ARM-LABEL: t16:363; ARM: @ %bb.0: @ %entry364; ARM-NEXT: cmp r0, #0365; ARM-NEXT: mov r2, #2366; ARM-NEXT: movweq r2, #5367; ARM-NEXT: mov r0, #4368; ARM-NEXT: cmp r1, #0369; ARM-NEXT: movweq r0, #3370; ARM-NEXT: and r0, r0, r2371; ARM-NEXT: bx lr372;373; T2-LABEL: t16:374; T2: @ %bb.0: @ %entry375; T2-NEXT: cmp r0, #0376; T2-NEXT: mov.w r2, #2377; T2-NEXT: mov.w r0, #4378; T2-NEXT: it eq379; T2-NEXT: moveq r2, #5380; T2-NEXT: cmp r1, #0381; T2-NEXT: it eq382; T2-NEXT: moveq r0, #3383; T2-NEXT: ands r0, r2384; T2-NEXT: bx lr385entry:386 %cmp = icmp eq i32 %x, 0387 %cond = select i1 %cmp, i32 5, i32 2388 %cmp1 = icmp eq i32 %y, 0389 %cond2 = select i1 %cmp1, i32 3, i32 4390 %and = and i32 %cond2, %cond391 ret i32 %and392}393 394define i32 @t17(i32 %x, i32 %y) #0 {395; ARM-LABEL: t17:396; ARM: @ %bb.0: @ %entry397; ARM-NEXT: cmn r0, #1398; ARM-NEXT: mov r2, #2399; ARM-NEXT: movweq r2, #5400; ARM-NEXT: mov r0, #4401; ARM-NEXT: cmn r1, #1402; ARM-NEXT: movweq r0, #3403; ARM-NEXT: and r0, r0, r2404; ARM-NEXT: bx lr405;406; T2-LABEL: t17:407; T2: @ %bb.0: @ %entry408; T2-NEXT: adds r0, #1409; T2-NEXT: mov.w r0, #2410; T2-NEXT: it eq411; T2-NEXT: moveq r0, #5412; T2-NEXT: adds r1, #1413; T2-NEXT: mov.w r1, #4414; T2-NEXT: it eq415; T2-NEXT: moveq r1, #3416; T2-NEXT: ands r0, r1417; T2-NEXT: bx lr418entry:419 %cmp = icmp eq i32 %x, -1420 %cond = select i1 %cmp, i32 5, i32 2421 %cmp1 = icmp eq i32 %y, -1422 %cond2 = select i1 %cmp1, i32 3, i32 4423 %and = and i32 %cond2, %cond424 ret i32 %and425}426 427define i32 @t18(i32 %x, i32 %y) #0 {428; ARM-LABEL: t18:429; ARM: @ %bb.0: @ %entry430; ARM-NEXT: mov r1, #2431; ARM-NEXT: cmp r0, #0432; ARM-NEXT: movwne r1, #5433; ARM-NEXT: mov r2, #4434; ARM-NEXT: cmn r0, #1435; ARM-NEXT: movwne r2, #3436; ARM-NEXT: and r0, r2, r1437; ARM-NEXT: bx lr438;439; T2-LABEL: t18:440; T2: @ %bb.0: @ %entry441; T2-NEXT: movs r1, #2442; T2-NEXT: cmp r0, #0443; T2-NEXT: it ne444; T2-NEXT: movne r1, #5445; T2-NEXT: adds r0, #1446; T2-NEXT: mov.w r0, #4447; T2-NEXT: it ne448; T2-NEXT: movne r0, #3449; T2-NEXT: ands r0, r1450; T2-NEXT: bx lr451entry:452 %cmp = icmp ne i32 %x, 0453 %cond = select i1 %cmp, i32 5, i32 2454 %cmp1 = icmp ne i32 %x, -1455 %cond2 = select i1 %cmp1, i32 3, i32 4456 %and = and i32 %cond2, %cond457 ret i32 %and458}459 460define i32 @t19(i32 %x, i32 %y) #0 {461; ARM-LABEL: t19:462; ARM: @ %bb.0: @ %entry463; ARM-NEXT: cmp r0, #0464; ARM-NEXT: mov r2, #2465; ARM-NEXT: movwne r2, #5466; ARM-NEXT: mov r0, #4467; ARM-NEXT: cmp r1, #0468; ARM-NEXT: movwne r0, #3469; ARM-NEXT: orr r0, r0, r2470; ARM-NEXT: bx lr471;472; T2-LABEL: t19:473; T2: @ %bb.0: @ %entry474; T2-NEXT: cmp r0, #0475; T2-NEXT: mov.w r2, #2476; T2-NEXT: mov.w r0, #4477; T2-NEXT: it ne478; T2-NEXT: movne r2, #5479; T2-NEXT: cmp r1, #0480; T2-NEXT: it ne481; T2-NEXT: movne r0, #3482; T2-NEXT: orrs r0, r2483; T2-NEXT: bx lr484entry:485 %cmp = icmp ne i32 %x, 0486 %cond = select i1 %cmp, i32 5, i32 2487 %cmp1 = icmp ne i32 %y, 0488 %cond2 = select i1 %cmp1, i32 3, i32 4489 %or = or i32 %cond2, %cond490 ret i32 %or491}492 493define i32 @t20(i32 %x, i32 %y) #0 {494; ARM-LABEL: t20:495; ARM: @ %bb.0: @ %entry496; ARM-NEXT: cmn r0, #1497; ARM-NEXT: mov r2, #2498; ARM-NEXT: movwne r2, #5499; ARM-NEXT: mov r0, #4500; ARM-NEXT: cmn r1, #1501; ARM-NEXT: movwne r0, #3502; ARM-NEXT: orr r0, r0, r2503; ARM-NEXT: bx lr504;505; T2-LABEL: t20:506; T2: @ %bb.0: @ %entry507; T2-NEXT: adds r0, #1508; T2-NEXT: mov.w r0, #2509; T2-NEXT: it ne510; T2-NEXT: movne r0, #5511; T2-NEXT: adds r1, #1512; T2-NEXT: mov.w r1, #4513; T2-NEXT: it ne514; T2-NEXT: movne r1, #3515; T2-NEXT: orrs r0, r1516; T2-NEXT: bx lr517entry:518 %cmp = icmp ne i32 %x, -1519 %cond = select i1 %cmp, i32 5, i32 2520 %cmp1 = icmp ne i32 %y, -1521 %cond2 = select i1 %cmp1, i32 3, i32 4522 %or = or i32 %cond2, %cond523 ret i32 %or524}525 526define <2 x i32> @t21(<2 x i32> %lhs, <2 x i32> %rhs) {527; CHECK-LABEL: t21:528; CHECK: @ %bb.0:529; CHECK-NEXT: vmov d16, r2, r3530; CHECK-NEXT: vmov d17, r0, r1531; CHECK-NEXT: vceq.i32 d16, d17, d16532; CHECK-NEXT: vmvn d16, d16533; CHECK-NEXT: vshl.i32 d16, d16, #31534; CHECK-NEXT: vshr.s32 d16, d16, #31535; CHECK-NEXT: vmov r0, r1, d16536; CHECK-NEXT: bx lr537 %tst = icmp eq <2 x i32> %lhs, %rhs538 %ntst = xor <2 x i1> %tst, <i1 1 , i1 undef>539 %btst = sext <2 x i1> %ntst to <2 x i32>540 ret <2 x i32> %btst541}542