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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=arm-eabi -mcpu=cortex-a8 | FileCheck %s3 4define zeroext i1 @ne_neg1_and_ne_zero(i32 %x) nounwind {5; CHECK-LABEL: ne_neg1_and_ne_zero:6; CHECK: @ %bb.0:7; CHECK-NEXT: add r1, r0, #18; CHECK-NEXT: mov r0, #09; CHECK-NEXT: cmp r1, #110; CHECK-NEXT: movwhi r0, #111; CHECK-NEXT: bx lr12 %cmp1 = icmp ne i32 %x, -113 %cmp2 = icmp ne i32 %x, 014 %and = and i1 %cmp1, %cmp215 ret i1 %and16}17 18; PR32401 - https://bugs.llvm.org/show_bug.cgi?id=3240119 20define zeroext i1 @and_eq(i32 %a, i32 %b, i32 %c, i32 %d) nounwind {21; CHECK-LABEL: and_eq:22; CHECK: @ %bb.0:23; CHECK: eor r2, r2, r324; CHECK: eor r0, r0, r125; CHECK: orr r0, r0, r226; CHECK: clz r0, r027; CHECK: lsr r0, r0, #528; CHECK: bx lr29 %cmp1 = icmp eq i32 %a, %b30 %cmp2 = icmp eq i32 %c, %d31 %and = and i1 %cmp1, %cmp232 ret i1 %and33}34 35define zeroext i1 @or_ne(i32 %a, i32 %b, i32 %c, i32 %d) nounwind {36; CHECK-LABEL: or_ne:37; CHECK: @ %bb.0:38; CHECK-NEXT: eor r2, r2, r339; CHECK-NEXT: eor r0, r0, r140; CHECK-NEXT: orrs r0, r0, r241; CHECK-NEXT: movwne r0, #142; CHECK-NEXT: bx lr43 %cmp1 = icmp ne i32 %a, %b44 %cmp2 = icmp ne i32 %c, %d45 %or = or i1 %cmp1, %cmp246 ret i1 %or47}48 49define <4 x i1> @and_eq_vec(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c, <4 x i32> %d) nounwind {50; CHECK-LABEL: and_eq_vec:51; CHECK: @ %bb.0:52; CHECK-NEXT: .save {r11, lr}53; CHECK-NEXT: push {r11, lr}54; CHECK-NEXT: vmov d19, r2, r355; CHECK-NEXT: add r12, sp, #4056; CHECK-NEXT: add lr, sp, #857; CHECK-NEXT: vmov d18, r0, r158; CHECK-NEXT: vld1.64 {d16, d17}, [lr]59; CHECK-NEXT: add r0, sp, #2460; CHECK-NEXT: vld1.64 {d20, d21}, [r12]61; CHECK-NEXT: vceq.i32 q8, q9, q862; CHECK-NEXT: vld1.64 {d22, d23}, [r0]63; CHECK-NEXT: vceq.i32 q9, q11, q1064; CHECK-NEXT: vand q8, q8, q965; CHECK-NEXT: vmovn.i32 d16, q866; CHECK-NEXT: vmov r0, r1, d1667; CHECK-NEXT: pop {r11, pc}68 %cmp1 = icmp eq <4 x i32> %a, %b69 %cmp2 = icmp eq <4 x i32> %c, %d70 %and = and <4 x i1> %cmp1, %cmp271 ret <4 x i1> %and72}73 74