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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=armv7-linux-gnueabihf %s -o - | FileCheck %s --check-prefixes=CHECK-COMMON,CHECK-ARM3; RUN: llc -mtriple=armv7eb-linux-gnueabihf %s -o - | FileCheck %s --check-prefixes=CHECK-BE4; RUN: llc -mtriple=thumbv7-linux-gnueabihf %s -o - | FileCheck %s --check-prefixes=CHECK-COMMON,CHECK-THUMB5; RUN: llc -mtriple=thumbv7m %s -o - | FileCheck %s --check-prefixes=CHECK-COMMON,CHECK-THUMB6; RUN: llc -mtriple=thumbv7m -mattr=+strict-align %s -o - | FileCheck %s --check-prefixes=CHECK-COMMON,CHECK-ALIGN7; RUN: llc -mtriple=thumbv6m %s -o - | FileCheck %s --check-prefix=CHECK-V6M8 9@array = weak global [4 x i32] zeroinitializer10 11define i32 @test_lshr_and1(i32 %x) {12; CHECK-COMMON-LABEL: test_lshr_and1:13; CHECK-COMMON: @ %bb.0: @ %entry14; CHECK-COMMON-NEXT: movw r1, :lower16:array15; CHECK-COMMON-NEXT: and r0, r0, #1216; CHECK-COMMON-NEXT: movt r1, :upper16:array17; CHECK-COMMON-NEXT: ldr r0, [r1, r0]18; CHECK-COMMON-NEXT: bx lr19;20; CHECK-BE-LABEL: test_lshr_and1:21; CHECK-BE: @ %bb.0: @ %entry22; CHECK-BE-NEXT: movw r1, :lower16:array23; CHECK-BE-NEXT: and r0, r0, #1224; CHECK-BE-NEXT: movt r1, :upper16:array25; CHECK-BE-NEXT: ldr r0, [r1, r0]26; CHECK-BE-NEXT: bx lr27;28; CHECK-V6M-LABEL: test_lshr_and1:29; CHECK-V6M: @ %bb.0: @ %entry30; CHECK-V6M-NEXT: movs r1, #1231; CHECK-V6M-NEXT: ands r1, r032; CHECK-V6M-NEXT: ldr r0, .LCPI0_033; CHECK-V6M-NEXT: ldr r0, [r0, r1]34; CHECK-V6M-NEXT: bx lr35; CHECK-V6M-NEXT: .p2align 236; CHECK-V6M-NEXT: @ %bb.1:37; CHECK-V6M-NEXT: .LCPI0_0:38; CHECK-V6M-NEXT: .long array39entry:40 %tmp2 = lshr i32 %x, 241 %tmp3 = and i32 %tmp2, 342 %tmp4 = getelementptr [4 x i32], ptr @array, i32 0, i32 %tmp343 %tmp5 = load i32, ptr %tmp4, align 444 ret i32 %tmp545}46define i32 @test_lshr_and2(i32 %x) {47; CHECK-ARM-LABEL: test_lshr_and2:48; CHECK-ARM: @ %bb.0: @ %entry49; CHECK-ARM-NEXT: ubfx r0, r0, #1, #1550; CHECK-ARM-NEXT: add r0, r0, r051; CHECK-ARM-NEXT: bx lr52;53; CHECK-BE-LABEL: test_lshr_and2:54; CHECK-BE: @ %bb.0: @ %entry55; CHECK-BE-NEXT: ubfx r0, r0, #1, #1556; CHECK-BE-NEXT: add r0, r0, r057; CHECK-BE-NEXT: bx lr58;59; CHECK-THUMB-LABEL: test_lshr_and2:60; CHECK-THUMB: @ %bb.0: @ %entry61; CHECK-THUMB-NEXT: ubfx r0, r0, #1, #1562; CHECK-THUMB-NEXT: add r0, r063; CHECK-THUMB-NEXT: bx lr64;65; CHECK-ALIGN-LABEL: test_lshr_and2:66; CHECK-ALIGN: @ %bb.0: @ %entry67; CHECK-ALIGN-NEXT: ubfx r0, r0, #1, #1568; CHECK-ALIGN-NEXT: add r0, r069; CHECK-ALIGN-NEXT: bx lr70;71; CHECK-V6M-LABEL: test_lshr_and2:72; CHECK-V6M: @ %bb.0: @ %entry73; CHECK-V6M-NEXT: lsls r0, r0, #1674; CHECK-V6M-NEXT: lsrs r0, r0, #1775; CHECK-V6M-NEXT: adds r0, r0, r076; CHECK-V6M-NEXT: bx lr77entry:78 %a = and i32 %x, 6553479 %b = lshr i32 %a, 180 %c = and i32 %x, 6553581 %d = lshr i32 %c, 182 %e = add i32 %b, %d83 ret i32 %e84}85 86define arm_aapcscc i32 @test_lshr_load1(ptr %a) {87; CHECK-COMMON-LABEL: test_lshr_load1:88; CHECK-COMMON: @ %bb.0: @ %entry89; CHECK-COMMON-NEXT: ldrb r0, [r0, #1]90; CHECK-COMMON-NEXT: bx lr91;92; CHECK-BE-LABEL: test_lshr_load1:93; CHECK-BE: @ %bb.0: @ %entry94; CHECK-BE-NEXT: ldrb r0, [r0]95; CHECK-BE-NEXT: bx lr96;97; CHECK-V6M-LABEL: test_lshr_load1:98; CHECK-V6M: @ %bb.0: @ %entry99; CHECK-V6M-NEXT: ldrb r0, [r0, #1]100; CHECK-V6M-NEXT: bx lr101entry:102 %0 = load i16, ptr %a, align 2103 %conv1 = zext i16 %0 to i32104 %1 = lshr i32 %conv1, 8105 ret i32 %1106}107 108define arm_aapcscc i32 @test_lshr_load1_sext(ptr %a) {109; CHECK-ARM-LABEL: test_lshr_load1_sext:110; CHECK-ARM: @ %bb.0: @ %entry111; CHECK-ARM-NEXT: ldrsh r0, [r0]112; CHECK-ARM-NEXT: lsr r0, r0, #8113; CHECK-ARM-NEXT: bx lr114;115; CHECK-BE-LABEL: test_lshr_load1_sext:116; CHECK-BE: @ %bb.0: @ %entry117; CHECK-BE-NEXT: ldrsh r0, [r0]118; CHECK-BE-NEXT: lsr r0, r0, #8119; CHECK-BE-NEXT: bx lr120;121; CHECK-THUMB-LABEL: test_lshr_load1_sext:122; CHECK-THUMB: @ %bb.0: @ %entry123; CHECK-THUMB-NEXT: ldrsh.w r0, [r0]124; CHECK-THUMB-NEXT: lsrs r0, r0, #8125; CHECK-THUMB-NEXT: bx lr126;127; CHECK-ALIGN-LABEL: test_lshr_load1_sext:128; CHECK-ALIGN: @ %bb.0: @ %entry129; CHECK-ALIGN-NEXT: ldrsh.w r0, [r0]130; CHECK-ALIGN-NEXT: lsrs r0, r0, #8131; CHECK-ALIGN-NEXT: bx lr132;133; CHECK-V6M-LABEL: test_lshr_load1_sext:134; CHECK-V6M: @ %bb.0: @ %entry135; CHECK-V6M-NEXT: movs r1, #0136; CHECK-V6M-NEXT: ldrsh r0, [r0, r1]137; CHECK-V6M-NEXT: lsrs r0, r0, #8138; CHECK-V6M-NEXT: bx lr139entry:140 %0 = load i16, ptr %a, align 2141 %conv1 = sext i16 %0 to i32142 %1 = lshr i32 %conv1, 8143 ret i32 %1144}145 146define arm_aapcscc i32 @test_lshr_load1_fail(ptr %a) {147; CHECK-ARM-LABEL: test_lshr_load1_fail:148; CHECK-ARM: @ %bb.0: @ %entry149; CHECK-ARM-NEXT: ldrh r0, [r0]150; CHECK-ARM-NEXT: lsr r0, r0, #9151; CHECK-ARM-NEXT: bx lr152;153; CHECK-BE-LABEL: test_lshr_load1_fail:154; CHECK-BE: @ %bb.0: @ %entry155; CHECK-BE-NEXT: ldrh r0, [r0]156; CHECK-BE-NEXT: lsr r0, r0, #9157; CHECK-BE-NEXT: bx lr158;159; CHECK-THUMB-LABEL: test_lshr_load1_fail:160; CHECK-THUMB: @ %bb.0: @ %entry161; CHECK-THUMB-NEXT: ldrh r0, [r0]162; CHECK-THUMB-NEXT: lsrs r0, r0, #9163; CHECK-THUMB-NEXT: bx lr164;165; CHECK-ALIGN-LABEL: test_lshr_load1_fail:166; CHECK-ALIGN: @ %bb.0: @ %entry167; CHECK-ALIGN-NEXT: ldrh r0, [r0]168; CHECK-ALIGN-NEXT: lsrs r0, r0, #9169; CHECK-ALIGN-NEXT: bx lr170;171; CHECK-V6M-LABEL: test_lshr_load1_fail:172; CHECK-V6M: @ %bb.0: @ %entry173; CHECK-V6M-NEXT: ldrh r0, [r0]174; CHECK-V6M-NEXT: lsrs r0, r0, #9175; CHECK-V6M-NEXT: bx lr176entry:177 %0 = load i16, ptr %a, align 2178 %conv1 = zext i16 %0 to i32179 %1 = lshr i32 %conv1, 9180 ret i32 %1181}182 183define arm_aapcscc i32 @test_lshr_load32(ptr %a) {184; CHECK-ARM-LABEL: test_lshr_load32:185; CHECK-ARM: @ %bb.0: @ %entry186; CHECK-ARM-NEXT: ldr r0, [r0]187; CHECK-ARM-NEXT: lsr r0, r0, #8188; CHECK-ARM-NEXT: bx lr189;190; CHECK-BE-LABEL: test_lshr_load32:191; CHECK-BE: @ %bb.0: @ %entry192; CHECK-BE-NEXT: ldr r0, [r0]193; CHECK-BE-NEXT: lsr r0, r0, #8194; CHECK-BE-NEXT: bx lr195;196; CHECK-THUMB-LABEL: test_lshr_load32:197; CHECK-THUMB: @ %bb.0: @ %entry198; CHECK-THUMB-NEXT: ldr r0, [r0]199; CHECK-THUMB-NEXT: lsrs r0, r0, #8200; CHECK-THUMB-NEXT: bx lr201;202; CHECK-ALIGN-LABEL: test_lshr_load32:203; CHECK-ALIGN: @ %bb.0: @ %entry204; CHECK-ALIGN-NEXT: ldr r0, [r0]205; CHECK-ALIGN-NEXT: lsrs r0, r0, #8206; CHECK-ALIGN-NEXT: bx lr207;208; CHECK-V6M-LABEL: test_lshr_load32:209; CHECK-V6M: @ %bb.0: @ %entry210; CHECK-V6M-NEXT: ldr r0, [r0]211; CHECK-V6M-NEXT: lsrs r0, r0, #8212; CHECK-V6M-NEXT: bx lr213entry:214 %0 = load i32, ptr %a, align 4215 %1 = lshr i32 %0, 8216 ret i32 %1217}218 219define arm_aapcscc i32 @test_lshr_load32_2(ptr %a) {220; CHECK-COMMON-LABEL: test_lshr_load32_2:221; CHECK-COMMON: @ %bb.0: @ %entry222; CHECK-COMMON-NEXT: ldrh r0, [r0, #2]223; CHECK-COMMON-NEXT: bx lr224;225; CHECK-BE-LABEL: test_lshr_load32_2:226; CHECK-BE: @ %bb.0: @ %entry227; CHECK-BE-NEXT: ldrh r0, [r0]228; CHECK-BE-NEXT: bx lr229;230; CHECK-V6M-LABEL: test_lshr_load32_2:231; CHECK-V6M: @ %bb.0: @ %entry232; CHECK-V6M-NEXT: ldrh r0, [r0, #2]233; CHECK-V6M-NEXT: bx lr234entry:235 %0 = load i32, ptr %a, align 4236 %1 = lshr i32 %0, 16237 ret i32 %1238}239 240define arm_aapcscc i32 @test_lshr_load32_1(ptr %a) {241; CHECK-COMMON-LABEL: test_lshr_load32_1:242; CHECK-COMMON: @ %bb.0: @ %entry243; CHECK-COMMON-NEXT: ldrb r0, [r0, #3]244; CHECK-COMMON-NEXT: bx lr245;246; CHECK-BE-LABEL: test_lshr_load32_1:247; CHECK-BE: @ %bb.0: @ %entry248; CHECK-BE-NEXT: ldrb r0, [r0]249; CHECK-BE-NEXT: bx lr250;251; CHECK-V6M-LABEL: test_lshr_load32_1:252; CHECK-V6M: @ %bb.0: @ %entry253; CHECK-V6M-NEXT: ldrb r0, [r0, #3]254; CHECK-V6M-NEXT: bx lr255entry:256 %0 = load i32, ptr %a, align 4257 %1 = lshr i32 %0, 24258 ret i32 %1259}260 261define arm_aapcscc i32 @test_lshr_load32_fail(ptr %a) {262; CHECK-ARM-LABEL: test_lshr_load32_fail:263; CHECK-ARM: @ %bb.0: @ %entry264; CHECK-ARM-NEXT: ldr r0, [r0]265; CHECK-ARM-NEXT: lsr r0, r0, #15266; CHECK-ARM-NEXT: bx lr267;268; CHECK-BE-LABEL: test_lshr_load32_fail:269; CHECK-BE: @ %bb.0: @ %entry270; CHECK-BE-NEXT: ldr r0, [r0]271; CHECK-BE-NEXT: lsr r0, r0, #15272; CHECK-BE-NEXT: bx lr273;274; CHECK-THUMB-LABEL: test_lshr_load32_fail:275; CHECK-THUMB: @ %bb.0: @ %entry276; CHECK-THUMB-NEXT: ldr r0, [r0]277; CHECK-THUMB-NEXT: lsrs r0, r0, #15278; CHECK-THUMB-NEXT: bx lr279;280; CHECK-ALIGN-LABEL: test_lshr_load32_fail:281; CHECK-ALIGN: @ %bb.0: @ %entry282; CHECK-ALIGN-NEXT: ldr r0, [r0]283; CHECK-ALIGN-NEXT: lsrs r0, r0, #15284; CHECK-ALIGN-NEXT: bx lr285;286; CHECK-V6M-LABEL: test_lshr_load32_fail:287; CHECK-V6M: @ %bb.0: @ %entry288; CHECK-V6M-NEXT: ldr r0, [r0]289; CHECK-V6M-NEXT: lsrs r0, r0, #15290; CHECK-V6M-NEXT: bx lr291entry:292 %0 = load i32, ptr %a, align 4293 %1 = lshr i32 %0, 15294 ret i32 %1295}296 297define arm_aapcscc i32 @test_lshr_load64_4_unaligned(ptr %a) {298; CHECK-ARM-LABEL: test_lshr_load64_4_unaligned:299; CHECK-ARM: @ %bb.0: @ %entry300; CHECK-ARM-NEXT: ldr r0, [r0, #2]301; CHECK-ARM-NEXT: bx lr302;303; CHECK-BE-LABEL: test_lshr_load64_4_unaligned:304; CHECK-BE: @ %bb.0: @ %entry305; CHECK-BE-NEXT: ldr r0, [r0, #2]306; CHECK-BE-NEXT: bx lr307;308; CHECK-THUMB-LABEL: test_lshr_load64_4_unaligned:309; CHECK-THUMB: @ %bb.0: @ %entry310; CHECK-THUMB-NEXT: ldr.w r0, [r0, #2]311; CHECK-THUMB-NEXT: bx lr312;313; CHECK-ALIGN-LABEL: test_lshr_load64_4_unaligned:314; CHECK-ALIGN: @ %bb.0: @ %entry315; CHECK-ALIGN-NEXT: ldr r1, [r0, #4]316; CHECK-ALIGN-NEXT: ldrh r0, [r0, #2]317; CHECK-ALIGN-NEXT: orr.w r0, r0, r1, lsl #16318; CHECK-ALIGN-NEXT: bx lr319;320; CHECK-V6M-LABEL: test_lshr_load64_4_unaligned:321; CHECK-V6M: @ %bb.0: @ %entry322; CHECK-V6M-NEXT: ldrh r1, [r0, #2]323; CHECK-V6M-NEXT: ldr r0, [r0, #4]324; CHECK-V6M-NEXT: lsls r0, r0, #16325; CHECK-V6M-NEXT: adds r0, r1, r0326; CHECK-V6M-NEXT: bx lr327entry:328 %0 = load i64, ptr %a, align 8329 %1 = lshr i64 %0, 16330 %conv = trunc i64 %1 to i32331 ret i32 %conv332}333 334define arm_aapcscc i32 @test_lshr_load64_1_lsb(ptr %a) {335; CHECK-ARM-LABEL: test_lshr_load64_1_lsb:336; CHECK-ARM: @ %bb.0: @ %entry337; CHECK-ARM-NEXT: ldr r0, [r0, #3]338; CHECK-ARM-NEXT: bx lr339;340; CHECK-BE-LABEL: test_lshr_load64_1_lsb:341; CHECK-BE: @ %bb.0: @ %entry342; CHECK-BE-NEXT: ldr r0, [r0, #1]343; CHECK-BE-NEXT: bx lr344;345; CHECK-THUMB-LABEL: test_lshr_load64_1_lsb:346; CHECK-THUMB: @ %bb.0: @ %entry347; CHECK-THUMB-NEXT: ldr.w r0, [r0, #3]348; CHECK-THUMB-NEXT: bx lr349;350; CHECK-ALIGN-LABEL: test_lshr_load64_1_lsb:351; CHECK-ALIGN: @ %bb.0: @ %entry352; CHECK-ALIGN-NEXT: ldr r1, [r0, #4]353; CHECK-ALIGN-NEXT: ldrb r0, [r0, #3]354; CHECK-ALIGN-NEXT: orr.w r0, r0, r1, lsl #8355; CHECK-ALIGN-NEXT: bx lr356;357; CHECK-V6M-LABEL: test_lshr_load64_1_lsb:358; CHECK-V6M: @ %bb.0: @ %entry359; CHECK-V6M-NEXT: ldrb r1, [r0, #3]360; CHECK-V6M-NEXT: ldr r0, [r0, #4]361; CHECK-V6M-NEXT: lsls r0, r0, #8362; CHECK-V6M-NEXT: adds r0, r1, r0363; CHECK-V6M-NEXT: bx lr364entry:365 %0 = load i64, ptr %a, align 8366 %1 = lshr i64 %0, 24367 %conv = trunc i64 %1 to i32368 ret i32 %conv369}370 371define arm_aapcscc i32 @test_lshr_load64_1_msb(ptr %a) {372; CHECK-COMMON-LABEL: test_lshr_load64_1_msb:373; CHECK-COMMON: @ %bb.0: @ %entry374; CHECK-COMMON-NEXT: ldrb r0, [r0, #7]375; CHECK-COMMON-NEXT: bx lr376;377; CHECK-BE-LABEL: test_lshr_load64_1_msb:378; CHECK-BE: @ %bb.0: @ %entry379; CHECK-BE-NEXT: ldrb r0, [r0]380; CHECK-BE-NEXT: bx lr381;382; CHECK-V6M-LABEL: test_lshr_load64_1_msb:383; CHECK-V6M: @ %bb.0: @ %entry384; CHECK-V6M-NEXT: ldrb r0, [r0, #7]385; CHECK-V6M-NEXT: bx lr386entry:387 %0 = load i64, ptr %a, align 8388 %1 = lshr i64 %0, 56389 %conv = trunc i64 %1 to i32390 ret i32 %conv391}392 393define arm_aapcscc i32 @test_lshr_load64_4(ptr %a) {394; CHECK-COMMON-LABEL: test_lshr_load64_4:395; CHECK-COMMON: @ %bb.0: @ %entry396; CHECK-COMMON-NEXT: ldr r0, [r0, #4]397; CHECK-COMMON-NEXT: bx lr398;399; CHECK-BE-LABEL: test_lshr_load64_4:400; CHECK-BE: @ %bb.0: @ %entry401; CHECK-BE-NEXT: ldr r0, [r0]402; CHECK-BE-NEXT: bx lr403;404; CHECK-V6M-LABEL: test_lshr_load64_4:405; CHECK-V6M: @ %bb.0: @ %entry406; CHECK-V6M-NEXT: ldr r0, [r0, #4]407; CHECK-V6M-NEXT: bx lr408entry:409 %0 = load i64, ptr %a, align 8410 %1 = lshr i64 %0, 32411 %conv = trunc i64 %1 to i32412 ret i32 %conv413}414 415define arm_aapcscc i32 @test_lshr_load64_2(ptr %a) {416; CHECK-COMMON-LABEL: test_lshr_load64_2:417; CHECK-COMMON: @ %bb.0: @ %entry418; CHECK-COMMON-NEXT: ldrh r0, [r0, #6]419; CHECK-COMMON-NEXT: bx lr420;421; CHECK-BE-LABEL: test_lshr_load64_2:422; CHECK-BE: @ %bb.0: @ %entry423; CHECK-BE-NEXT: ldrh r0, [r0]424; CHECK-BE-NEXT: bx lr425;426; CHECK-V6M-LABEL: test_lshr_load64_2:427; CHECK-V6M: @ %bb.0: @ %entry428; CHECK-V6M-NEXT: ldrh r0, [r0, #6]429; CHECK-V6M-NEXT: bx lr430entry:431 %0 = load i64, ptr %a, align 8432 %1 = lshr i64 %0, 48433 %conv = trunc i64 %1 to i32434 ret i32 %conv435}436 437define arm_aapcscc i32 @test_lshr_load4_fail(ptr %a) {438; CHECK-ARM-LABEL: test_lshr_load4_fail:439; CHECK-ARM: @ %bb.0: @ %entry440; CHECK-ARM-NEXT: ldr r0, [r0, #1]441; CHECK-ARM-NEXT: bx lr442;443; CHECK-BE-LABEL: test_lshr_load4_fail:444; CHECK-BE: @ %bb.0: @ %entry445; CHECK-BE-NEXT: ldr r0, [r0, #3]446; CHECK-BE-NEXT: bx lr447;448; CHECK-THUMB-LABEL: test_lshr_load4_fail:449; CHECK-THUMB: @ %bb.0: @ %entry450; CHECK-THUMB-NEXT: ldr.w r0, [r0, #1]451; CHECK-THUMB-NEXT: bx lr452;453; CHECK-ALIGN-LABEL: test_lshr_load4_fail:454; CHECK-ALIGN: @ %bb.0: @ %entry455; CHECK-ALIGN-NEXT: ldrd r0, r1, [r0]456; CHECK-ALIGN-NEXT: lsrs r0, r0, #8457; CHECK-ALIGN-NEXT: orr.w r0, r0, r1, lsl #24458; CHECK-ALIGN-NEXT: bx lr459;460; CHECK-V6M-LABEL: test_lshr_load4_fail:461; CHECK-V6M: @ %bb.0: @ %entry462; CHECK-V6M-NEXT: ldr r1, [r0]463; CHECK-V6M-NEXT: ldr r0, [r0, #4]464; CHECK-V6M-NEXT: lsls r0, r0, #24465; CHECK-V6M-NEXT: lsrs r1, r1, #8466; CHECK-V6M-NEXT: adds r0, r1, r0467; CHECK-V6M-NEXT: bx lr468entry:469 %0 = load i64, ptr %a, align 8470 %1 = lshr i64 %0, 8471 %conv = trunc i64 %1 to i32472 ret i32 %conv473}474 475define arm_aapcscc void @test_shift7_mask8(ptr nocapture %p) {476; CHECK-COMMON-LABEL: test_shift7_mask8:477; CHECK-COMMON: @ %bb.0: @ %entry478; CHECK-COMMON-NEXT: ldr r1, [r0]479; CHECK-COMMON-NEXT: ubfx r1, r1, #7, #8480; CHECK-COMMON-NEXT: str r1, [r0]481; CHECK-COMMON-NEXT: bx lr482;483; CHECK-BE-LABEL: test_shift7_mask8:484; CHECK-BE: @ %bb.0: @ %entry485; CHECK-BE-NEXT: ldr r1, [r0]486; CHECK-BE-NEXT: ubfx r1, r1, #7, #8487; CHECK-BE-NEXT: str r1, [r0]488; CHECK-BE-NEXT: bx lr489;490; CHECK-V6M-LABEL: test_shift7_mask8:491; CHECK-V6M: @ %bb.0: @ %entry492; CHECK-V6M-NEXT: ldr r1, [r0]493; CHECK-V6M-NEXT: lsrs r1, r1, #7494; CHECK-V6M-NEXT: uxtb r1, r1495; CHECK-V6M-NEXT: str r1, [r0]496; CHECK-V6M-NEXT: bx lr497entry:498 %0 = load i32, ptr %p, align 4499 %shl = lshr i32 %0, 7500 %and = and i32 %shl, 255501 store i32 %and, ptr %p, align 4502 ret void503}504 505define arm_aapcscc void @test_shift8_mask8(ptr nocapture %p) {506; CHECK-COMMON-LABEL: test_shift8_mask8:507; CHECK-COMMON: @ %bb.0: @ %entry508; CHECK-COMMON-NEXT: ldrb r1, [r0, #1]509; CHECK-COMMON-NEXT: str r1, [r0]510; CHECK-COMMON-NEXT: bx lr511;512; CHECK-BE-LABEL: test_shift8_mask8:513; CHECK-BE: @ %bb.0: @ %entry514; CHECK-BE-NEXT: ldrb r1, [r0, #2]515; CHECK-BE-NEXT: str r1, [r0]516; CHECK-BE-NEXT: bx lr517;518; CHECK-V6M-LABEL: test_shift8_mask8:519; CHECK-V6M: @ %bb.0: @ %entry520; CHECK-V6M-NEXT: ldrb r1, [r0, #1]521; CHECK-V6M-NEXT: str r1, [r0]522; CHECK-V6M-NEXT: bx lr523entry:524 %0 = load i32, ptr %p, align 4525 %shl = lshr i32 %0, 8526 %and = and i32 %shl, 255527 store i32 %and, ptr %p, align 4528 ret void529}530 531define arm_aapcscc void @test_shift8_mask7(ptr nocapture %p) {532; CHECK-COMMON-LABEL: test_shift8_mask7:533; CHECK-COMMON: @ %bb.0: @ %entry534; CHECK-COMMON-NEXT: ldr r1, [r0]535; CHECK-COMMON-NEXT: ubfx r1, r1, #8, #7536; CHECK-COMMON-NEXT: str r1, [r0]537; CHECK-COMMON-NEXT: bx lr538;539; CHECK-BE-LABEL: test_shift8_mask7:540; CHECK-BE: @ %bb.0: @ %entry541; CHECK-BE-NEXT: ldr r1, [r0]542; CHECK-BE-NEXT: ubfx r1, r1, #8, #7543; CHECK-BE-NEXT: str r1, [r0]544; CHECK-BE-NEXT: bx lr545;546; CHECK-V6M-LABEL: test_shift8_mask7:547; CHECK-V6M: @ %bb.0: @ %entry548; CHECK-V6M-NEXT: ldr r1, [r0]549; CHECK-V6M-NEXT: lsls r1, r1, #17550; CHECK-V6M-NEXT: lsrs r1, r1, #25551; CHECK-V6M-NEXT: str r1, [r0]552; CHECK-V6M-NEXT: bx lr553entry:554 %0 = load i32, ptr %p, align 4555 %shl = lshr i32 %0, 8556 %and = and i32 %shl, 127557 store i32 %and, ptr %p, align 4558 ret void559}560 561define arm_aapcscc void @test_shift9_mask8(ptr nocapture %p) {562; CHECK-COMMON-LABEL: test_shift9_mask8:563; CHECK-COMMON: @ %bb.0: @ %entry564; CHECK-COMMON-NEXT: ldr r1, [r0]565; CHECK-COMMON-NEXT: ubfx r1, r1, #9, #8566; CHECK-COMMON-NEXT: str r1, [r0]567; CHECK-COMMON-NEXT: bx lr568;569; CHECK-BE-LABEL: test_shift9_mask8:570; CHECK-BE: @ %bb.0: @ %entry571; CHECK-BE-NEXT: ldr r1, [r0]572; CHECK-BE-NEXT: ubfx r1, r1, #9, #8573; CHECK-BE-NEXT: str r1, [r0]574; CHECK-BE-NEXT: bx lr575;576; CHECK-V6M-LABEL: test_shift9_mask8:577; CHECK-V6M: @ %bb.0: @ %entry578; CHECK-V6M-NEXT: ldr r1, [r0]579; CHECK-V6M-NEXT: lsrs r1, r1, #9580; CHECK-V6M-NEXT: uxtb r1, r1581; CHECK-V6M-NEXT: str r1, [r0]582; CHECK-V6M-NEXT: bx lr583entry:584 %0 = load i32, ptr %p, align 4585 %shl = lshr i32 %0, 9586 %and = and i32 %shl, 255587 store i32 %and, ptr %p, align 4588 ret void589}590 591define arm_aapcscc void @test_shift8_mask16(ptr nocapture %p) {592; CHECK-ARM-LABEL: test_shift8_mask16:593; CHECK-ARM: @ %bb.0: @ %entry594; CHECK-ARM-NEXT: ldrh r1, [r0, #1]595; CHECK-ARM-NEXT: str r1, [r0]596; CHECK-ARM-NEXT: bx lr597;598; CHECK-BE-LABEL: test_shift8_mask16:599; CHECK-BE: @ %bb.0: @ %entry600; CHECK-BE-NEXT: ldrh r1, [r0, #1]601; CHECK-BE-NEXT: str r1, [r0]602; CHECK-BE-NEXT: bx lr603;604; CHECK-THUMB-LABEL: test_shift8_mask16:605; CHECK-THUMB: @ %bb.0: @ %entry606; CHECK-THUMB-NEXT: ldrh.w r1, [r0, #1]607; CHECK-THUMB-NEXT: str r1, [r0]608; CHECK-THUMB-NEXT: bx lr609;610; CHECK-ALIGN-LABEL: test_shift8_mask16:611; CHECK-ALIGN: @ %bb.0: @ %entry612; CHECK-ALIGN-NEXT: ldr r1, [r0]613; CHECK-ALIGN-NEXT: ubfx r1, r1, #8, #16614; CHECK-ALIGN-NEXT: str r1, [r0]615; CHECK-ALIGN-NEXT: bx lr616;617; CHECK-V6M-LABEL: test_shift8_mask16:618; CHECK-V6M: @ %bb.0: @ %entry619; CHECK-V6M-NEXT: ldr r1, [r0]620; CHECK-V6M-NEXT: lsrs r1, r1, #8621; CHECK-V6M-NEXT: uxth r1, r1622; CHECK-V6M-NEXT: str r1, [r0]623; CHECK-V6M-NEXT: bx lr624entry:625 %0 = load i32, ptr %p, align 4626 %shl = lshr i32 %0, 8627 %and = and i32 %shl, 65535628 store i32 %and, ptr %p, align 4629 ret void630}631 632define arm_aapcscc void @test_shift15_mask16(ptr nocapture %p) {633; CHECK-COMMON-LABEL: test_shift15_mask16:634; CHECK-COMMON: @ %bb.0: @ %entry635; CHECK-COMMON-NEXT: ldr r1, [r0]636; CHECK-COMMON-NEXT: ubfx r1, r1, #15, #16637; CHECK-COMMON-NEXT: str r1, [r0]638; CHECK-COMMON-NEXT: bx lr639;640; CHECK-BE-LABEL: test_shift15_mask16:641; CHECK-BE: @ %bb.0: @ %entry642; CHECK-BE-NEXT: ldr r1, [r0]643; CHECK-BE-NEXT: ubfx r1, r1, #15, #16644; CHECK-BE-NEXT: str r1, [r0]645; CHECK-BE-NEXT: bx lr646;647; CHECK-V6M-LABEL: test_shift15_mask16:648; CHECK-V6M: @ %bb.0: @ %entry649; CHECK-V6M-NEXT: ldr r1, [r0]650; CHECK-V6M-NEXT: lsrs r1, r1, #15651; CHECK-V6M-NEXT: uxth r1, r1652; CHECK-V6M-NEXT: str r1, [r0]653; CHECK-V6M-NEXT: bx lr654entry:655 %0 = load i32, ptr %p, align 4656 %shl = lshr i32 %0, 15657 %and = and i32 %shl, 65535658 store i32 %and, ptr %p, align 4659 ret void660}661 662define arm_aapcscc void @test_shift16_mask15(ptr nocapture %p) {663; CHECK-COMMON-LABEL: test_shift16_mask15:664; CHECK-COMMON: @ %bb.0: @ %entry665; CHECK-COMMON-NEXT: ldrh r1, [r0, #2]666; CHECK-COMMON-NEXT: bfc r1, #15, #17667; CHECK-COMMON-NEXT: str r1, [r0]668; CHECK-COMMON-NEXT: bx lr669;670; CHECK-BE-LABEL: test_shift16_mask15:671; CHECK-BE: @ %bb.0: @ %entry672; CHECK-BE-NEXT: ldrh r1, [r0]673; CHECK-BE-NEXT: bfc r1, #15, #17674; CHECK-BE-NEXT: str r1, [r0]675; CHECK-BE-NEXT: bx lr676;677; CHECK-V6M-LABEL: test_shift16_mask15:678; CHECK-V6M: @ %bb.0: @ %entry679; CHECK-V6M-NEXT: ldrh r1, [r0, #2]680; CHECK-V6M-NEXT: ldr r2, .LCPI21_0681; CHECK-V6M-NEXT: ands r2, r1682; CHECK-V6M-NEXT: str r2, [r0]683; CHECK-V6M-NEXT: bx lr684; CHECK-V6M-NEXT: .p2align 2685; CHECK-V6M-NEXT: @ %bb.1:686; CHECK-V6M-NEXT: .LCPI21_0:687; CHECK-V6M-NEXT: .long 32767 @ 0x7fff688entry:689 %0 = load i32, ptr %p, align 4690 %shl = lshr i32 %0, 16691 %and = and i32 %shl, 32767692 store i32 %and, ptr %p, align 4693 ret void694}695 696define arm_aapcscc void @test_shift8_mask24(ptr nocapture %p) {697; CHECK-ARM-LABEL: test_shift8_mask24:698; CHECK-ARM: @ %bb.0: @ %entry699; CHECK-ARM-NEXT: ldr r1, [r0]700; CHECK-ARM-NEXT: lsr r1, r1, #8701; CHECK-ARM-NEXT: str r1, [r0]702; CHECK-ARM-NEXT: bx lr703;704; CHECK-BE-LABEL: test_shift8_mask24:705; CHECK-BE: @ %bb.0: @ %entry706; CHECK-BE-NEXT: ldr r1, [r0]707; CHECK-BE-NEXT: lsr r1, r1, #8708; CHECK-BE-NEXT: str r1, [r0]709; CHECK-BE-NEXT: bx lr710;711; CHECK-THUMB-LABEL: test_shift8_mask24:712; CHECK-THUMB: @ %bb.0: @ %entry713; CHECK-THUMB-NEXT: ldr r1, [r0]714; CHECK-THUMB-NEXT: lsrs r1, r1, #8715; CHECK-THUMB-NEXT: str r1, [r0]716; CHECK-THUMB-NEXT: bx lr717;718; CHECK-ALIGN-LABEL: test_shift8_mask24:719; CHECK-ALIGN: @ %bb.0: @ %entry720; CHECK-ALIGN-NEXT: ldr r1, [r0]721; CHECK-ALIGN-NEXT: lsrs r1, r1, #8722; CHECK-ALIGN-NEXT: str r1, [r0]723; CHECK-ALIGN-NEXT: bx lr724;725; CHECK-V6M-LABEL: test_shift8_mask24:726; CHECK-V6M: @ %bb.0: @ %entry727; CHECK-V6M-NEXT: ldr r1, [r0]728; CHECK-V6M-NEXT: lsrs r1, r1, #8729; CHECK-V6M-NEXT: str r1, [r0]730; CHECK-V6M-NEXT: bx lr731entry:732 %0 = load i32, ptr %p, align 4733 %shl = lshr i32 %0, 8734 %and = and i32 %shl, 16777215735 store i32 %and, ptr %p, align 4736 ret void737}738 739define arm_aapcscc void @test_shift24_mask16(ptr nocapture %p) {740; CHECK-COMMON-LABEL: test_shift24_mask16:741; CHECK-COMMON: @ %bb.0: @ %entry742; CHECK-COMMON-NEXT: ldrb r1, [r0, #3]743; CHECK-COMMON-NEXT: str r1, [r0]744; CHECK-COMMON-NEXT: bx lr745;746; CHECK-BE-LABEL: test_shift24_mask16:747; CHECK-BE: @ %bb.0: @ %entry748; CHECK-BE-NEXT: ldrb r1, [r0]749; CHECK-BE-NEXT: str r1, [r0]750; CHECK-BE-NEXT: bx lr751;752; CHECK-V6M-LABEL: test_shift24_mask16:753; CHECK-V6M: @ %bb.0: @ %entry754; CHECK-V6M-NEXT: ldrb r1, [r0, #3]755; CHECK-V6M-NEXT: str r1, [r0]756; CHECK-V6M-NEXT: bx lr757entry:758 %0 = load i32, ptr %p, align 4759 %shl = lshr i32 %0, 24760 %and = and i32 %shl, 65535761 store i32 %and, ptr %p, align 4762 ret void763}764 765define arm_aapcscc void @test_sext_shift8_mask8(ptr %p, ptr %q) {766; CHECK-COMMON-LABEL: test_sext_shift8_mask8:767; CHECK-COMMON: @ %bb.0: @ %entry768; CHECK-COMMON-NEXT: ldrb r0, [r0, #1]769; CHECK-COMMON-NEXT: str r0, [r1]770; CHECK-COMMON-NEXT: bx lr771;772; CHECK-BE-LABEL: test_sext_shift8_mask8:773; CHECK-BE: @ %bb.0: @ %entry774; CHECK-BE-NEXT: ldrb r0, [r0]775; CHECK-BE-NEXT: str r0, [r1]776; CHECK-BE-NEXT: bx lr777;778; CHECK-V6M-LABEL: test_sext_shift8_mask8:779; CHECK-V6M: @ %bb.0: @ %entry780; CHECK-V6M-NEXT: ldrb r0, [r0, #1]781; CHECK-V6M-NEXT: str r0, [r1]782; CHECK-V6M-NEXT: bx lr783entry:784 %0 = load i16, ptr %p, align 4785 %1 = sext i16 %0 to i32786 %shl = lshr i32 %1, 8787 %and = and i32 %shl, 255788 store i32 %and, ptr %q, align 4789 ret void790}791 792define arm_aapcscc void @test_sext_shift8_mask16(ptr %p, ptr %q) {793; CHECK-ARM-LABEL: test_sext_shift8_mask16:794; CHECK-ARM: @ %bb.0: @ %entry795; CHECK-ARM-NEXT: ldrsh r0, [r0]796; CHECK-ARM-NEXT: ubfx r0, r0, #8, #16797; CHECK-ARM-NEXT: str r0, [r1]798; CHECK-ARM-NEXT: bx lr799;800; CHECK-BE-LABEL: test_sext_shift8_mask16:801; CHECK-BE: @ %bb.0: @ %entry802; CHECK-BE-NEXT: ldrsh r0, [r0]803; CHECK-BE-NEXT: ubfx r0, r0, #8, #16804; CHECK-BE-NEXT: str r0, [r1]805; CHECK-BE-NEXT: bx lr806;807; CHECK-THUMB-LABEL: test_sext_shift8_mask16:808; CHECK-THUMB: @ %bb.0: @ %entry809; CHECK-THUMB-NEXT: ldrsh.w r0, [r0]810; CHECK-THUMB-NEXT: ubfx r0, r0, #8, #16811; CHECK-THUMB-NEXT: str r0, [r1]812; CHECK-THUMB-NEXT: bx lr813;814; CHECK-ALIGN-LABEL: test_sext_shift8_mask16:815; CHECK-ALIGN: @ %bb.0: @ %entry816; CHECK-ALIGN-NEXT: ldrsh.w r0, [r0]817; CHECK-ALIGN-NEXT: ubfx r0, r0, #8, #16818; CHECK-ALIGN-NEXT: str r0, [r1]819; CHECK-ALIGN-NEXT: bx lr820;821; CHECK-V6M-LABEL: test_sext_shift8_mask16:822; CHECK-V6M: @ %bb.0: @ %entry823; CHECK-V6M-NEXT: movs r2, #0824; CHECK-V6M-NEXT: ldrsh r0, [r0, r2]825; CHECK-V6M-NEXT: lsrs r0, r0, #8826; CHECK-V6M-NEXT: uxth r0, r0827; CHECK-V6M-NEXT: str r0, [r1]828; CHECK-V6M-NEXT: bx lr829entry:830 %0 = load i16, ptr %p, align 4831 %1 = sext i16 %0 to i32832 %shl = lshr i32 %1, 8833 %and = and i32 %shl, 65535834 store i32 %and, ptr %q, align 4835 ret void836}837 838define i1 @trunc_i64_mask_srl(i32 zeroext %AttrArgNo, ptr %ptr) {839; CHECK-ARM-LABEL: trunc_i64_mask_srl:840; CHECK-ARM: @ %bb.0: @ %entry841; CHECK-ARM-NEXT: ldrh r2, [r1, #4]842; CHECK-ARM-NEXT: mov r1, #0843; CHECK-ARM-NEXT: cmp r2, r0844; CHECK-ARM-NEXT: movwhi r1, #1845; CHECK-ARM-NEXT: mov r0, r1846; CHECK-ARM-NEXT: bx lr847;848; CHECK-BE-LABEL: trunc_i64_mask_srl:849; CHECK-BE: @ %bb.0: @ %entry850; CHECK-BE-NEXT: ldrh r2, [r1, #2]851; CHECK-BE-NEXT: mov r1, #0852; CHECK-BE-NEXT: cmp r2, r0853; CHECK-BE-NEXT: movwhi r1, #1854; CHECK-BE-NEXT: mov r0, r1855; CHECK-BE-NEXT: bx lr856;857; CHECK-THUMB-LABEL: trunc_i64_mask_srl:858; CHECK-THUMB: @ %bb.0: @ %entry859; CHECK-THUMB-NEXT: ldrh r2, [r1, #4]860; CHECK-THUMB-NEXT: movs r1, #0861; CHECK-THUMB-NEXT: cmp r2, r0862; CHECK-THUMB-NEXT: it hi863; CHECK-THUMB-NEXT: movhi r1, #1864; CHECK-THUMB-NEXT: mov r0, r1865; CHECK-THUMB-NEXT: bx lr866;867; CHECK-ALIGN-LABEL: trunc_i64_mask_srl:868; CHECK-ALIGN: @ %bb.0: @ %entry869; CHECK-ALIGN-NEXT: ldrh r2, [r1, #4]870; CHECK-ALIGN-NEXT: movs r1, #0871; CHECK-ALIGN-NEXT: cmp r2, r0872; CHECK-ALIGN-NEXT: it hi873; CHECK-ALIGN-NEXT: movhi r1, #1874; CHECK-ALIGN-NEXT: mov r0, r1875; CHECK-ALIGN-NEXT: bx lr876;877; CHECK-V6M-LABEL: trunc_i64_mask_srl:878; CHECK-V6M: @ %bb.0: @ %entry879; CHECK-V6M-NEXT: ldrh r1, [r1, #4]880; CHECK-V6M-NEXT: cmp r1, r0881; CHECK-V6M-NEXT: bhi .LBB26_2882; CHECK-V6M-NEXT: @ %bb.1: @ %entry883; CHECK-V6M-NEXT: movs r0, #0884; CHECK-V6M-NEXT: bx lr885; CHECK-V6M-NEXT: .LBB26_2:886; CHECK-V6M-NEXT: movs r0, #1887; CHECK-V6M-NEXT: bx lr888entry:889 %bf.load.i = load i64, ptr %ptr, align 8890 %bf.lshr.i = lshr i64 %bf.load.i, 32891 %0 = trunc i64 %bf.lshr.i to i32892 %bf.cast.i = and i32 %0, 65535893 %cmp.i = icmp ugt i32 %bf.cast.i, %AttrArgNo894 ret i1 %cmp.i895}896 897define i64 @or_tree_with_shifts_i64(i64 %a, i64 %b, i64 %c, i64 %d) {898; CHECK-ARM-LABEL: or_tree_with_shifts_i64:899; CHECK-ARM: @ %bb.0:900; CHECK-ARM-NEXT: .save {r11, lr}901; CHECK-ARM-NEXT: push {r11, lr}902; CHECK-ARM-NEXT: ldr lr, [sp, #16]903; CHECK-ARM-NEXT: orr r0, r0, r2, lsl #16904; CHECK-ARM-NEXT: ldr r12, [sp, #8]905; CHECK-ARM-NEXT: orr r3, lr, r3906; CHECK-ARM-NEXT: orr r1, r1, r3, lsl #16907; CHECK-ARM-NEXT: orr r1, r1, r2, lsr #16908; CHECK-ARM-NEXT: orr r1, r1, r12909; CHECK-ARM-NEXT: pop {r11, pc}910;911; CHECK-BE-LABEL: or_tree_with_shifts_i64:912; CHECK-BE: @ %bb.0:913; CHECK-BE-NEXT: .save {r11, lr}914; CHECK-BE-NEXT: push {r11, lr}915; CHECK-BE-NEXT: ldr lr, [sp, #20]916; CHECK-BE-NEXT: orr r1, r1, r3, lsl #16917; CHECK-BE-NEXT: ldr r12, [sp, #12]918; CHECK-BE-NEXT: orr r2, lr, r2919; CHECK-BE-NEXT: orr r0, r0, r2, lsl #16920; CHECK-BE-NEXT: orr r0, r0, r3, lsr #16921; CHECK-BE-NEXT: orr r0, r0, r12922; CHECK-BE-NEXT: pop {r11, pc}923;924; CHECK-ALIGN-LABEL: or_tree_with_shifts_i64:925; CHECK-ALIGN: @ %bb.0:926; CHECK-ALIGN-NEXT: ldr.w r12, [sp, #8]927; CHECK-ALIGN-NEXT: orr.w r0, r0, r2, lsl #16928; CHECK-ALIGN-NEXT: orr.w r3, r3, r12929; CHECK-ALIGN-NEXT: orr.w r1, r1, r3, lsl #16930; CHECK-ALIGN-NEXT: orr.w r1, r1, r2, lsr #16931; CHECK-ALIGN-NEXT: ldr r2, [sp]932; CHECK-ALIGN-NEXT: orrs r1, r2933; CHECK-ALIGN-NEXT: bx lr934;935; CHECK-V6M-LABEL: or_tree_with_shifts_i64:936; CHECK-V6M: @ %bb.0:937; CHECK-V6M-NEXT: push {r4, lr}938; CHECK-V6M-NEXT: lsls r4, r2, #16939; CHECK-V6M-NEXT: orrs r0, r4940; CHECK-V6M-NEXT: ldr r4, [sp, #16]941; CHECK-V6M-NEXT: orrs r4, r3942; CHECK-V6M-NEXT: lsls r3, r4, #16943; CHECK-V6M-NEXT: orrs r1, r3944; CHECK-V6M-NEXT: lsrs r2, r2, #16945; CHECK-V6M-NEXT: orrs r1, r2946; CHECK-V6M-NEXT: ldr r2, [sp, #8]947; CHECK-V6M-NEXT: orrs r1, r2948; CHECK-V6M-NEXT: pop {r4, pc}949 %b.shifted = shl i64 %b, 16950 %c.shifted = shl i64 %c, 32951 %d.shifted = shl i64 %d, 48952 %or.ad = or i64 %a, %d.shifted953 %or.adb = or i64 %or.ad, %b.shifted954 %or.adbc = or i64 %or.adb, %c.shifted955 ret i64 %or.adbc956}957 958define i32 @or_tree_with_shifts_i32(i32 %a, i32 %b, i32 %c, i32 %d) {959; CHECK-ARM-LABEL: or_tree_with_shifts_i32:960; CHECK-ARM: @ %bb.0:961; CHECK-ARM-NEXT: orr r0, r0, r2962; CHECK-ARM-NEXT: orr r0, r1, r0, lsl #16963; CHECK-ARM-NEXT: orr r0, r0, r3964; CHECK-ARM-NEXT: bx lr965;966; CHECK-BE-LABEL: or_tree_with_shifts_i32:967; CHECK-BE: @ %bb.0:968; CHECK-BE-NEXT: orr r0, r0, r2969; CHECK-BE-NEXT: orr r0, r1, r0, lsl #16970; CHECK-BE-NEXT: orr r0, r0, r3971; CHECK-BE-NEXT: bx lr972;973; CHECK-THUMB-LABEL: or_tree_with_shifts_i32:974; CHECK-THUMB: @ %bb.0:975; CHECK-THUMB-NEXT: orrs r0, r2976; CHECK-THUMB-NEXT: orr.w r0, r1, r0, lsl #16977; CHECK-THUMB-NEXT: orrs r0, r3978; CHECK-THUMB-NEXT: bx lr979;980; CHECK-ALIGN-LABEL: or_tree_with_shifts_i32:981; CHECK-ALIGN: @ %bb.0:982; CHECK-ALIGN-NEXT: orrs r0, r2983; CHECK-ALIGN-NEXT: orr.w r0, r1, r0, lsl #16984; CHECK-ALIGN-NEXT: orrs r0, r3985; CHECK-ALIGN-NEXT: bx lr986;987; CHECK-V6M-LABEL: or_tree_with_shifts_i32:988; CHECK-V6M: @ %bb.0:989; CHECK-V6M-NEXT: orrs r0, r2990; CHECK-V6M-NEXT: lsls r0, r0, #16991; CHECK-V6M-NEXT: orrs r0, r1992; CHECK-V6M-NEXT: orrs r0, r3993; CHECK-V6M-NEXT: bx lr994 %a.shifted = shl i32 %a, 16995 %c.shifted = shl i32 %c, 16996 %or.ab = or i32 %a.shifted, %b997 %or.cd = or i32 %c.shifted, %d998 %r = or i32 %or.ab, %or.cd999 ret i32 %r1000}1001 1002define i32 @xor_tree_with_shifts_i32(i32 %a, i32 %b, i32 %c, i32 %d) {1003; CHECK-ARM-LABEL: xor_tree_with_shifts_i32:1004; CHECK-ARM: @ %bb.0:1005; CHECK-ARM-NEXT: eor r0, r0, r21006; CHECK-ARM-NEXT: eor r0, r1, r0, lsr #161007; CHECK-ARM-NEXT: eor r0, r0, r31008; CHECK-ARM-NEXT: bx lr1009;1010; CHECK-BE-LABEL: xor_tree_with_shifts_i32:1011; CHECK-BE: @ %bb.0:1012; CHECK-BE-NEXT: eor r0, r0, r21013; CHECK-BE-NEXT: eor r0, r1, r0, lsr #161014; CHECK-BE-NEXT: eor r0, r0, r31015; CHECK-BE-NEXT: bx lr1016;1017; CHECK-THUMB-LABEL: xor_tree_with_shifts_i32:1018; CHECK-THUMB: @ %bb.0:1019; CHECK-THUMB-NEXT: eors r0, r21020; CHECK-THUMB-NEXT: eor.w r0, r1, r0, lsr #161021; CHECK-THUMB-NEXT: eors r0, r31022; CHECK-THUMB-NEXT: bx lr1023;1024; CHECK-ALIGN-LABEL: xor_tree_with_shifts_i32:1025; CHECK-ALIGN: @ %bb.0:1026; CHECK-ALIGN-NEXT: eors r0, r21027; CHECK-ALIGN-NEXT: eor.w r0, r1, r0, lsr #161028; CHECK-ALIGN-NEXT: eors r0, r31029; CHECK-ALIGN-NEXT: bx lr1030;1031; CHECK-V6M-LABEL: xor_tree_with_shifts_i32:1032; CHECK-V6M: @ %bb.0:1033; CHECK-V6M-NEXT: eors r0, r21034; CHECK-V6M-NEXT: lsrs r0, r0, #161035; CHECK-V6M-NEXT: eors r0, r11036; CHECK-V6M-NEXT: eors r0, r31037; CHECK-V6M-NEXT: bx lr1038 %a.shifted = lshr i32 %a, 161039 %c.shifted = lshr i32 %c, 161040 %xor.ab = xor i32 %a.shifted, %b1041 %xor.cd = xor i32 %d, %c.shifted1042 %r = xor i32 %xor.ab, %xor.cd1043 ret i32 %r1044}1045 1046define i32 @and_tree_with_shifts_i32(i32 %a, i32 %b, i32 %c, i32 %d) {1047; CHECK-ARM-LABEL: and_tree_with_shifts_i32:1048; CHECK-ARM: @ %bb.0:1049; CHECK-ARM-NEXT: and r0, r0, r21050; CHECK-ARM-NEXT: and r0, r1, r0, asr #161051; CHECK-ARM-NEXT: and r0, r0, r31052; CHECK-ARM-NEXT: bx lr1053;1054; CHECK-BE-LABEL: and_tree_with_shifts_i32:1055; CHECK-BE: @ %bb.0:1056; CHECK-BE-NEXT: and r0, r0, r21057; CHECK-BE-NEXT: and r0, r1, r0, asr #161058; CHECK-BE-NEXT: and r0, r0, r31059; CHECK-BE-NEXT: bx lr1060;1061; CHECK-THUMB-LABEL: and_tree_with_shifts_i32:1062; CHECK-THUMB: @ %bb.0:1063; CHECK-THUMB-NEXT: ands r0, r21064; CHECK-THUMB-NEXT: and.w r0, r1, r0, asr #161065; CHECK-THUMB-NEXT: ands r0, r31066; CHECK-THUMB-NEXT: bx lr1067;1068; CHECK-ALIGN-LABEL: and_tree_with_shifts_i32:1069; CHECK-ALIGN: @ %bb.0:1070; CHECK-ALIGN-NEXT: ands r0, r21071; CHECK-ALIGN-NEXT: and.w r0, r1, r0, asr #161072; CHECK-ALIGN-NEXT: ands r0, r31073; CHECK-ALIGN-NEXT: bx lr1074;1075; CHECK-V6M-LABEL: and_tree_with_shifts_i32:1076; CHECK-V6M: @ %bb.0:1077; CHECK-V6M-NEXT: ands r0, r21078; CHECK-V6M-NEXT: asrs r0, r0, #161079; CHECK-V6M-NEXT: ands r0, r11080; CHECK-V6M-NEXT: ands r0, r31081; CHECK-V6M-NEXT: bx lr1082 %a.shifted = ashr i32 %a, 161083 %c.shifted = ashr i32 %c, 161084 %and.ab = and i32 %b, %a.shifted1085 %and.cd = and i32 %c.shifted, %d1086 %r = and i32 %and.ab, %and.cd1087 ret i32 %r1088}1089 1090define i32 @logic_tree_with_shifts_var_i32(i32 %a, i32 %b, i32 %c, i32 %d, i32 %s) {1091; CHECK-ARM-LABEL: logic_tree_with_shifts_var_i32:1092; CHECK-ARM: @ %bb.0:1093; CHECK-ARM-NEXT: ldr r12, [sp]1094; CHECK-ARM-NEXT: orr r0, r0, r21095; CHECK-ARM-NEXT: orr r0, r1, r0, lsl r121096; CHECK-ARM-NEXT: orr r0, r0, r31097; CHECK-ARM-NEXT: bx lr1098;1099; CHECK-BE-LABEL: logic_tree_with_shifts_var_i32:1100; CHECK-BE: @ %bb.0:1101; CHECK-BE-NEXT: ldr r12, [sp]1102; CHECK-BE-NEXT: orr r0, r0, r21103; CHECK-BE-NEXT: orr r0, r1, r0, lsl r121104; CHECK-BE-NEXT: orr r0, r0, r31105; CHECK-BE-NEXT: bx lr1106;1107; CHECK-ALIGN-LABEL: logic_tree_with_shifts_var_i32:1108; CHECK-ALIGN: @ %bb.0:1109; CHECK-ALIGN-NEXT: orrs r0, r21110; CHECK-ALIGN-NEXT: ldr r2, [sp]1111; CHECK-ALIGN-NEXT: lsls r0, r21112; CHECK-ALIGN-NEXT: orrs r0, r11113; CHECK-ALIGN-NEXT: orrs r0, r31114; CHECK-ALIGN-NEXT: bx lr1115;1116; CHECK-V6M-LABEL: logic_tree_with_shifts_var_i32:1117; CHECK-V6M: @ %bb.0:1118; CHECK-V6M-NEXT: orrs r0, r21119; CHECK-V6M-NEXT: ldr r2, [sp]1120; CHECK-V6M-NEXT: lsls r0, r21121; CHECK-V6M-NEXT: orrs r0, r11122; CHECK-V6M-NEXT: orrs r0, r31123; CHECK-V6M-NEXT: bx lr1124 %a.shifted = shl i32 %a, %s1125 %c.shifted = shl i32 %c, %s1126 %or.ab = or i32 %b, %a.shifted1127 %or.cd = or i32 %d, %c.shifted1128 %r = or i32 %or.ab, %or.cd1129 ret i32 %r1130}1131 1132define i32 @logic_tree_with_mismatching_shifts_i32(i32 %a, i32 %b, i32 %c, i32 %d) {1133; CHECK-ARM-LABEL: logic_tree_with_mismatching_shifts_i32:1134; CHECK-ARM: @ %bb.0:1135; CHECK-ARM-NEXT: orr r2, r3, r2, lsl #161136; CHECK-ARM-NEXT: orr r0, r1, r0, lsl #151137; CHECK-ARM-NEXT: orr r0, r0, r21138; CHECK-ARM-NEXT: bx lr1139;1140; CHECK-BE-LABEL: logic_tree_with_mismatching_shifts_i32:1141; CHECK-BE: @ %bb.0:1142; CHECK-BE-NEXT: orr r2, r3, r2, lsl #161143; CHECK-BE-NEXT: orr r0, r1, r0, lsl #151144; CHECK-BE-NEXT: orr r0, r0, r21145; CHECK-BE-NEXT: bx lr1146;1147; CHECK-THUMB-LABEL: logic_tree_with_mismatching_shifts_i32:1148; CHECK-THUMB: @ %bb.0:1149; CHECK-THUMB-NEXT: orr.w r2, r3, r2, lsl #161150; CHECK-THUMB-NEXT: orr.w r0, r1, r0, lsl #151151; CHECK-THUMB-NEXT: orrs r0, r21152; CHECK-THUMB-NEXT: bx lr1153;1154; CHECK-ALIGN-LABEL: logic_tree_with_mismatching_shifts_i32:1155; CHECK-ALIGN: @ %bb.0:1156; CHECK-ALIGN-NEXT: orr.w r2, r3, r2, lsl #161157; CHECK-ALIGN-NEXT: orr.w r0, r1, r0, lsl #151158; CHECK-ALIGN-NEXT: orrs r0, r21159; CHECK-ALIGN-NEXT: bx lr1160;1161; CHECK-V6M-LABEL: logic_tree_with_mismatching_shifts_i32:1162; CHECK-V6M: @ %bb.0:1163; CHECK-V6M-NEXT: lsls r2, r2, #161164; CHECK-V6M-NEXT: orrs r2, r31165; CHECK-V6M-NEXT: lsls r0, r0, #151166; CHECK-V6M-NEXT: orrs r0, r11167; CHECK-V6M-NEXT: orrs r0, r21168; CHECK-V6M-NEXT: bx lr1169 %a.shifted = shl i32 %a, 151170 %c.shifted = shl i32 %c, 161171 %or.ab = or i32 %a.shifted, %b1172 %or.cd = or i32 %c.shifted, %d1173 %r = or i32 %or.ab, %or.cd1174 ret i32 %r1175}1176 1177define i32 @logic_tree_with_mismatching_shifts2_i32(i32 %a, i32 %b, i32 %c, i32 %d) {1178; CHECK-ARM-LABEL: logic_tree_with_mismatching_shifts2_i32:1179; CHECK-ARM: @ %bb.0:1180; CHECK-ARM-NEXT: orr r2, r3, r2, lsr #161181; CHECK-ARM-NEXT: orr r0, r1, r0, lsl #161182; CHECK-ARM-NEXT: orr r0, r0, r21183; CHECK-ARM-NEXT: bx lr1184;1185; CHECK-BE-LABEL: logic_tree_with_mismatching_shifts2_i32:1186; CHECK-BE: @ %bb.0:1187; CHECK-BE-NEXT: orr r2, r3, r2, lsr #161188; CHECK-BE-NEXT: orr r0, r1, r0, lsl #161189; CHECK-BE-NEXT: orr r0, r0, r21190; CHECK-BE-NEXT: bx lr1191;1192; CHECK-THUMB-LABEL: logic_tree_with_mismatching_shifts2_i32:1193; CHECK-THUMB: @ %bb.0:1194; CHECK-THUMB-NEXT: orr.w r2, r3, r2, lsr #161195; CHECK-THUMB-NEXT: orr.w r0, r1, r0, lsl #161196; CHECK-THUMB-NEXT: orrs r0, r21197; CHECK-THUMB-NEXT: bx lr1198;1199; CHECK-ALIGN-LABEL: logic_tree_with_mismatching_shifts2_i32:1200; CHECK-ALIGN: @ %bb.0:1201; CHECK-ALIGN-NEXT: orr.w r2, r3, r2, lsr #161202; CHECK-ALIGN-NEXT: orr.w r0, r1, r0, lsl #161203; CHECK-ALIGN-NEXT: orrs r0, r21204; CHECK-ALIGN-NEXT: bx lr1205;1206; CHECK-V6M-LABEL: logic_tree_with_mismatching_shifts2_i32:1207; CHECK-V6M: @ %bb.0:1208; CHECK-V6M-NEXT: lsrs r2, r2, #161209; CHECK-V6M-NEXT: orrs r2, r31210; CHECK-V6M-NEXT: lsls r0, r0, #161211; CHECK-V6M-NEXT: orrs r0, r11212; CHECK-V6M-NEXT: orrs r0, r21213; CHECK-V6M-NEXT: bx lr1214 %a.shifted = shl i32 %a, 161215 %c.shifted = lshr i32 %c, 161216 %or.ab = or i32 %a.shifted, %b1217 %or.cd = or i32 %c.shifted, %d1218 %r = or i32 %or.ab, %or.cd1219 ret i32 %r1220}1221 1222define <4 x i32> @or_tree_with_shifts_vec_i32(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c, <4 x i32> %d) {1223; CHECK-ARM-LABEL: or_tree_with_shifts_vec_i32:1224; CHECK-ARM: @ %bb.0:1225; CHECK-ARM-NEXT: vorr q8, q0, q21226; CHECK-ARM-NEXT: vshl.i32 q8, q8, #161227; CHECK-ARM-NEXT: vorr q8, q8, q11228; CHECK-ARM-NEXT: vorr q0, q8, q31229; CHECK-ARM-NEXT: bx lr1230;1231; CHECK-BE-LABEL: or_tree_with_shifts_vec_i32:1232; CHECK-BE: @ %bb.0:1233; CHECK-BE-NEXT: vrev64.32 q8, q21234; CHECK-BE-NEXT: vrev64.32 q9, q01235; CHECK-BE-NEXT: vorr q8, q9, q81236; CHECK-BE-NEXT: vrev64.32 q9, q11237; CHECK-BE-NEXT: vrev64.32 q10, q31238; CHECK-BE-NEXT: vshl.i32 q8, q8, #161239; CHECK-BE-NEXT: vorr q8, q8, q91240; CHECK-BE-NEXT: vorr q8, q8, q101241; CHECK-BE-NEXT: vrev64.32 q0, q81242; CHECK-BE-NEXT: bx lr1243 %a.shifted = shl <4 x i32> %a, <i32 16, i32 16, i32 16, i32 16>1244 %c.shifted = shl <4 x i32> %c, <i32 16, i32 16, i32 16, i32 16>1245 %or.ab = or <4 x i32> %a.shifted, %b1246 %or.cd = or <4 x i32> %c.shifted, %d1247 %r = or <4 x i32> %or.ab, %or.cd1248 ret <4 x i32> %r1249}1250 1251define <4 x i32> @or_tree_with_mismatching_shifts_vec_i32(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c, <4 x i32> %d) {1252; CHECK-ARM-LABEL: or_tree_with_mismatching_shifts_vec_i32:1253; CHECK-ARM: @ %bb.0:1254; CHECK-ARM-NEXT: vshl.i32 q8, q2, #171255; CHECK-ARM-NEXT: vshl.i32 q9, q0, #161256; CHECK-ARM-NEXT: vorr q8, q8, q31257; CHECK-ARM-NEXT: vorr q9, q9, q11258; CHECK-ARM-NEXT: vorr q0, q9, q81259; CHECK-ARM-NEXT: bx lr1260;1261; CHECK-BE-LABEL: or_tree_with_mismatching_shifts_vec_i32:1262; CHECK-BE: @ %bb.0:1263; CHECK-BE-NEXT: vrev64.32 q8, q21264; CHECK-BE-NEXT: vrev64.32 q9, q01265; CHECK-BE-NEXT: vshl.i32 q8, q8, #171266; CHECK-BE-NEXT: vrev64.32 q10, q31267; CHECK-BE-NEXT: vshl.i32 q9, q9, #161268; CHECK-BE-NEXT: vrev64.32 q11, q11269; CHECK-BE-NEXT: vorr q8, q8, q101270; CHECK-BE-NEXT: vorr q9, q9, q111271; CHECK-BE-NEXT: vorr q8, q9, q81272; CHECK-BE-NEXT: vrev64.32 q0, q81273; CHECK-BE-NEXT: bx lr1274 %a.shifted = shl <4 x i32> %a, <i32 16, i32 16, i32 16, i32 16>1275 %c.shifted = shl <4 x i32> %c, <i32 17, i32 17, i32 17, i32 17>1276 %or.ab = or <4 x i32> %a.shifted, %b1277 %or.cd = or <4 x i32> %c.shifted, %d1278 %r = or <4 x i32> %or.ab, %or.cd1279 ret <4 x i32> %r1280}1281 1282define arm_aapcscc i32 @test_shift15_and510(ptr nocapture %p) {1283; CHECK-ARM-LABEL: test_shift15_and510:1284; CHECK-ARM: @ %bb.0: @ %entry1285; CHECK-ARM-NEXT: ldrb r0, [r0, #2]1286; CHECK-ARM-NEXT: lsl r0, r0, #11287; CHECK-ARM-NEXT: bx lr1288;1289; CHECK-BE-LABEL: test_shift15_and510:1290; CHECK-BE: @ %bb.0: @ %entry1291; CHECK-BE-NEXT: ldrb r0, [r0, #1]1292; CHECK-BE-NEXT: lsl r0, r0, #11293; CHECK-BE-NEXT: bx lr1294;1295; CHECK-THUMB-LABEL: test_shift15_and510:1296; CHECK-THUMB: @ %bb.0: @ %entry1297; CHECK-THUMB-NEXT: ldrb r0, [r0, #2]1298; CHECK-THUMB-NEXT: lsls r0, r0, #11299; CHECK-THUMB-NEXT: bx lr1300;1301; CHECK-ALIGN-LABEL: test_shift15_and510:1302; CHECK-ALIGN: @ %bb.0: @ %entry1303; CHECK-ALIGN-NEXT: ldrb r0, [r0, #2]1304; CHECK-ALIGN-NEXT: lsls r0, r0, #11305; CHECK-ALIGN-NEXT: bx lr1306;1307; CHECK-V6M-LABEL: test_shift15_and510:1308; CHECK-V6M: @ %bb.0: @ %entry1309; CHECK-V6M-NEXT: ldrb r0, [r0, #2]1310; CHECK-V6M-NEXT: lsls r0, r0, #11311; CHECK-V6M-NEXT: bx lr1312entry:1313 %load = load i32, ptr %p, align 41314 %lshr = lshr i32 %load, 151315 %and = and i32 %lshr, 5101316 ret i32 %and1317}1318 1319define arm_aapcscc i32 @test_shift22_and1020(ptr nocapture %p) {1320; CHECK-ARM-LABEL: test_shift22_and1020:1321; CHECK-ARM: @ %bb.0: @ %entry1322; CHECK-ARM-NEXT: ldrb r0, [r0, #3]1323; CHECK-ARM-NEXT: lsl r0, r0, #21324; CHECK-ARM-NEXT: bx lr1325;1326; CHECK-BE-LABEL: test_shift22_and1020:1327; CHECK-BE: @ %bb.0: @ %entry1328; CHECK-BE-NEXT: ldrb r0, [r0]1329; CHECK-BE-NEXT: lsl r0, r0, #21330; CHECK-BE-NEXT: bx lr1331;1332; CHECK-THUMB-LABEL: test_shift22_and1020:1333; CHECK-THUMB: @ %bb.0: @ %entry1334; CHECK-THUMB-NEXT: ldrb r0, [r0, #3]1335; CHECK-THUMB-NEXT: lsls r0, r0, #21336; CHECK-THUMB-NEXT: bx lr1337;1338; CHECK-ALIGN-LABEL: test_shift22_and1020:1339; CHECK-ALIGN: @ %bb.0: @ %entry1340; CHECK-ALIGN-NEXT: ldrb r0, [r0, #3]1341; CHECK-ALIGN-NEXT: lsls r0, r0, #21342; CHECK-ALIGN-NEXT: bx lr1343;1344; CHECK-V6M-LABEL: test_shift22_and1020:1345; CHECK-V6M: @ %bb.0: @ %entry1346; CHECK-V6M-NEXT: ldrb r0, [r0, #3]1347; CHECK-V6M-NEXT: lsls r0, r0, #21348; CHECK-V6M-NEXT: bx lr1349entry:1350 %load = load i32, ptr %p, align 41351 %lshr = lshr i32 %load, 221352 %and = and i32 %lshr, 10201353 ret i32 %and1354}1355 1356define arm_aapcscc i32 @test_zext_shift5_and2040(ptr nocapture %p) {1357; CHECK-ARM-LABEL: test_zext_shift5_and2040:1358; CHECK-ARM: @ %bb.0: @ %entry1359; CHECK-ARM-NEXT: ldrb r0, [r0, #1]1360; CHECK-ARM-NEXT: lsl r0, r0, #31361; CHECK-ARM-NEXT: bx lr1362;1363; CHECK-BE-LABEL: test_zext_shift5_and2040:1364; CHECK-BE: @ %bb.0: @ %entry1365; CHECK-BE-NEXT: ldrb r0, [r0]1366; CHECK-BE-NEXT: lsl r0, r0, #31367; CHECK-BE-NEXT: bx lr1368;1369; CHECK-THUMB-LABEL: test_zext_shift5_and2040:1370; CHECK-THUMB: @ %bb.0: @ %entry1371; CHECK-THUMB-NEXT: ldrb r0, [r0, #1]1372; CHECK-THUMB-NEXT: lsls r0, r0, #31373; CHECK-THUMB-NEXT: bx lr1374;1375; CHECK-ALIGN-LABEL: test_zext_shift5_and2040:1376; CHECK-ALIGN: @ %bb.0: @ %entry1377; CHECK-ALIGN-NEXT: ldrb r0, [r0, #1]1378; CHECK-ALIGN-NEXT: lsls r0, r0, #31379; CHECK-ALIGN-NEXT: bx lr1380;1381; CHECK-V6M-LABEL: test_zext_shift5_and2040:1382; CHECK-V6M: @ %bb.0: @ %entry1383; CHECK-V6M-NEXT: ldrb r0, [r0, #1]1384; CHECK-V6M-NEXT: lsls r0, r0, #31385; CHECK-V6M-NEXT: bx lr1386entry:1387 %load = load i16, ptr %p, align 21388 %zext = zext i16 %load to i321389 %lshr = lshr i32 %zext, 51390 %and = and i32 %lshr, 20401391 ret i32 %and1392}1393