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1# RUN: llc -o /dev/null %s -mtriple=arm-eabi -mcpu=cortex-r52 -run-pass machine-scheduler -enable-misched -debug-only=machine-scheduler -misched-prera-direction=topdown 2>&1 | FileCheck %s --check-prefix=CHECK --check-prefix=TOPDOWN2# RUN: llc -o /dev/null %s -mtriple=arm-eabi -mcpu=cortex-r52 -run-pass machine-scheduler -enable-misched -debug-only=machine-scheduler -misched-prera-direction=bottomup 2>&1 | FileCheck %s --check-prefix=CHECK --check-prefix=BOTTOMUP3# RUN: llc -o /dev/null %s -mtriple=arm-eabi -mcpu=cortex-r52plus -run-pass machine-scheduler -enable-misched -debug-only=machine-scheduler -misched-prera-direction=topdown 2>&1 | FileCheck %s --check-prefix=CHECK --check-prefix=TOPDOWN4# RUN: llc -o /dev/null %s -mtriple=arm-eabi -mcpu=cortex-r52plus -run-pass machine-scheduler -enable-misched -debug-only=machine-scheduler -misched-prera-direction=bottomup 2>&1 | FileCheck %s --check-prefix=CHECK --check-prefix=BOTTOMUP5# REQUIRES: asserts6--- |7 ; ModuleID = 'foo.ll'8 source_filename = "foo.ll"9 target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"10 target triple = "arm---eabi"11 12 %struct.__neon_int8x8x4_t = type { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> }13 ; Function Attrs: nounwind14 define <8 x i8> @foo(ptr %A) {15 %tmp1 = call %struct.__neon_int8x8x4_t @llvm.arm.neon.vld4.v8i8.p0(ptr %A, i32 8)16 %tmp2 = extractvalue %struct.__neon_int8x8x4_t %tmp1, 017 %tmp3 = extractvalue %struct.__neon_int8x8x4_t %tmp1, 118 %tmp4 = add <8 x i8> %tmp2, %tmp319 ret <8 x i8> %tmp420 }21 declare %struct.__neon_int8x8x4_t @llvm.arm.neon.vld4.v8i8.p0(ptr, i32)22 23# CHECK: ********** MI Scheduling **********24# CHECK: ScheduleDAGMILive::schedule starting25# CHECK: SU(1): %1:qqpr = VLD4d8Pseudo %0:gpr, 8, 14, $noreg :: (load (s256) from %ir.A, align 8)26# CHECK: Latency : 827# CHECK: Single Issue : true;28# CHECK: SU(2): %4:dpr = VADDv8i8 %1.dsub_0:qqpr, %1.dsub_1:qqpr, 14, $noreg29# CHECK: Latency : 530# CHECK: Single Issue : false;31# CHECK: SU(3): %5:gpr, %6:gpr = VMOVRRD %4:dpr, 14, $noreg32# CHECK: Latency : 433# CHECK: Single Issue : false;34 35# TOPDOWN: Scheduling SU(1) %1:qqpr = VLD4d8Pseudo36# TOPDOWN: Bump cycle to end group37# TOPDOWN: Scheduling SU(2) %4:dpr = VADDv8i838 39# BOTTOMUP: Scheduling SU(2) %4:dpr = VADDv8i840# BOTTOMUP: Scheduling SU(1) %1:qqpr = VLD4d8Pseudo41# BOTTOMUP: Bump cycle to begin group42 43...44---45name: foo46alignment: 447exposesReturnsTwice: false48legalized: false49regBankSelected: false50selected: false51tracksRegLiveness: true52registers:53 - { id: 0, class: gpr }54 - { id: 1, class: qqpr }55 - { id: 2, class: dpr }56 - { id: 3, class: dpr }57 - { id: 4, class: dpr }58 - { id: 5, class: gpr }59 - { id: 6, class: gpr }60liveins:61 - { reg: '$r0', virtual-reg: '%0' }62frameInfo:63 isFrameAddressTaken: false64 isReturnAddressTaken: false65 hasStackMap: false66 hasPatchPoint: false67 stackSize: 068 offsetAdjustment: 069 maxAlignment: 070 adjustsStack: false71 hasCalls: false72 maxCallFrameSize: 073 hasOpaqueSPAdjustment: false74 hasVAStart: false75 hasMustTailInVarArgFunc: false76body: |77 bb.0 (%ir-block.0):78 liveins: $r079 80 %0 = COPY $r081 %1 = VLD4d8Pseudo %0, 8, 14, $noreg :: (load (s256) from %ir.A, align 8)82 %4 = VADDv8i8 %1.dsub_0, %1.dsub_1, 14, $noreg83 %5, %6 = VMOVRRD %4, 14, $noreg84 $r0 = COPY %585 $r1 = COPY %686 BX_RET 14, $noreg, implicit $r0, implicit killed $r187 88...89