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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -o - %s -mtriple=armv7-- -run-pass=machine-sink | FileCheck %s3 4name: sink-store-load-dep5tracksRegLiveness: true6stack:7 - { id: 0, type: default, size: 8, alignment: 8 }8body: |9 bb.0:10 ; CHECK-LABEL: name: sink-store-load-dep11 ; CHECK: bb.0:12 ; CHECK: [[LDRi12_:%[0-9]+]]:gpr = LDRi12 %stack.0, 0, 14 /* CC::al */, $noreg :: (load (s32))13 ; CHECK-NEXT: [[MOVi:%[0-9]+]]:gpr = MOVi 55296, 14 /* CC::al */, $noreg, $noreg14 ; CHECK-NEXT: [[ADDri1:%[0-9]+]]:gpr = ADDri [[LDRi12_:%[0-9]+]], 0, 14 /* CC::al */, $noreg, $noreg15 ; CHECK-NEXT: [[LDRH:%[0-9]+]]:gpr = LDRH killed [[ADDri1:%[0-9]+]], $noreg, 0, 14 /* CC::al */, $noreg :: (load (s16))16 ; CHECK-NEXT: [[MOVi1:%[0-9]+]]:gpr = MOVi 0, 14 /* CC::al */, $noreg, $noreg17 ; CHECK-NEXT: early-clobber %5:gpr = STRH_PRE [[MOVi:%[0-9]+]], [[LDRi12_:%[0-9]+]], [[MOVi1:%[0-9]+]], 0, 14 /* CC::al */, $noreg18 ; CHECK-NEXT: [[SUBri:%.*]]:gpr = SUBri killed [[LDRi12_:%[0-9]+]], 0, 14 /* CC::al */, $noreg, $noreg19 ; CHECK: bb.2:20 ; CHECK-NEXT: [[MOVi2:%[0-9]+]]:gpr = MOVi [[LDRH:%[0-9]+]], 14 /* CC::al */, $noreg, $noreg21 %0:gpr = LDRi12 %stack.0, 0, 14, $noreg :: (load (s32))22 %1:gpr = MOVi 55296, 14, $noreg, $noreg23 %2:gpr = ADDri %0:gpr, 0, 14, $noreg, $noreg24 %3:gpr = LDRH killed %2:gpr, $noreg, 0, 14, $noreg :: (load (s16))25 %4:gpr = MOVi 0, 14, $noreg, $noreg26 early-clobber %5:gpr = STRH_PRE %1:gpr, %0:gpr, %4:gpr, 0, 14, $noreg27 %6:gpr = SUBri killed %0:gpr, 0, 14, $noreg, $noreg28 CMPri %6:gpr, 0, 14, $noreg, implicit-def $cpsr29 Bcc %bb.2, 3, $cpsr30 B %bb.131 32 bb.1:33 %8:gpr = MOVi 0, 14, $noreg, $noreg34 $r0 = COPY %8:gpr35 BX_RET 14, $noreg, implicit $r036 37 bb.2:38 %9:gpr = MOVi %3:gpr, 14, $noreg, $noreg39 $r0 = COPY %9:gpr40 BX_RET 14, $noreg, implicit $r041...42