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1; RUN: llc < %s -mtriple=arm-none-eabi -mcpu=cortex-a8 2>&1 | FileCheck %s --check-prefix=ACORE2; RUN: not llc < %s -mtriple=thumb-none-eabi -mcpu=cortex-m4 2>&1 | FileCheck %s --check-prefix=MCORE3 4; MCORE: error: <unknown>:0:0: invalid register "cpsr" for llvm.read_register5; MCORE: error: <unknown>:0:0: invalid register "spsr_cxsf" for llvm.write_register6 7 8define i32 @read_cpsr() nounwind {9 ; ACORE-LABEL: read_cpsr:10 ; ACORE: mrs r0, apsr11 %reg = call i32 @llvm.read_register.i32(metadata !1)12 ret i32 %reg13}14 15define i32 @read_aclass_registers() nounwind {16entry:17 ; ACORE-LABEL: read_aclass_registers:18 ; ACORE: mrs r0, apsr19 ; ACORE: mrs r1, spsr20 21 %0 = call i32 @llvm.read_register.i32(metadata !0)22 %1 = call i32 @llvm.read_register.i32(metadata !1)23 %add1 = add i32 %1, %024 %2 = call i32 @llvm.read_register.i32(metadata !2)25 %add2 = add i32 %add1, %226 ret i32 %add227}28 29define void @write_aclass_registers(i32 %x) nounwind {30entry:31 ; ACORE-LABEL: write_aclass_registers:32 ; ACORE: msr APSR_nzcvq, r033 ; ACORE: msr APSR_g, r034 ; ACORE: msr APSR_nzcvqg, r035 ; ACORE: msr CPSR_c, r036 ; ACORE: msr CPSR_x, r037 ; ACORE: msr APSR_g, r038 ; ACORE: msr APSR_nzcvq, r039 ; ACORE: msr CPSR_fsxc, r040 ; ACORE: msr SPSR_c, r041 ; ACORE: msr SPSR_x, r042 ; ACORE: msr SPSR_s, r043 ; ACORE: msr SPSR_f, r044 ; ACORE: msr SPSR_fsxc, r045 46 call void @llvm.write_register.i32(metadata !3, i32 %x)47 call void @llvm.write_register.i32(metadata !4, i32 %x)48 call void @llvm.write_register.i32(metadata !5, i32 %x)49 call void @llvm.write_register.i32(metadata !6, i32 %x)50 call void @llvm.write_register.i32(metadata !7, i32 %x)51 call void @llvm.write_register.i32(metadata !8, i32 %x)52 call void @llvm.write_register.i32(metadata !9, i32 %x)53 call void @llvm.write_register.i32(metadata !10, i32 %x)54 call void @llvm.write_register.i32(metadata !11, i32 %x)55 call void @llvm.write_register.i32(metadata !12, i32 %x)56 call void @llvm.write_register.i32(metadata !13, i32 %x)57 call void @llvm.write_register.i32(metadata !14, i32 %x)58 call void @llvm.write_register.i32(metadata !15, i32 %x)59 ret void60}61 62declare i32 @llvm.read_register.i32(metadata) nounwind63declare void @llvm.write_register.i32(metadata, i32) nounwind64 65!0 = !{!"apsr"}66!1 = !{!"cpsr"}67!2 = !{!"spsr"}68!3 = !{!"apsr_nzcvq"}69!4 = !{!"apsr_g"}70!5 = !{!"apsr_nzcvqg"}71!6 = !{!"cpsr_c"}72!7 = !{!"cpsr_x"}73!8 = !{!"cpsr_s"}74!9 = !{!"cpsr_f"}75!10 = !{!"cpsr_cxsf"}76!11 = !{!"spsr_c"}77!12 = !{!"spsr_x"}78!13 = !{!"spsr_s"}79!14 = !{!"spsr_f"}80!15 = !{!"spsr_cxsf"}81