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1; RUN: llc < %s -mtriple=thumb-none-eabi -mcpu=cortex-m4 --show-mc-encoding 2>&1 | FileCheck %s --check-prefix=MCORE2; RUN: not llc < %s -mtriple=thumb-none-eabi -mcpu=cortex-m3 2>&1 | FileCheck %s --check-prefix=M3CORE3; RUN: not llc < %s -mtriple=arm-none-eabi -mcpu=cortex-a8 2>&1 | FileCheck %s --check-prefix=ACORE4 5; ACORE: error: <unknown>:0:0: invalid register "control" for llvm.write_register6; M3CORE: error: <unknown>:0:0: invalid register "xpsr_nzcvqg" for llvm.write_register7 8 9define i32 @read_mclass_registers() nounwind {10entry:11 ; MCORE-LABEL: read_mclass_registers:12 ; MCORE: mrs r0, apsr @ encoding: [0xef,0xf3,0x00,0x80]13 ; MCORE: mrs r1, iapsr @ encoding: [0xef,0xf3,0x01,0x81]14 ; MCORE: mrs r1, eapsr @ encoding: [0xef,0xf3,0x02,0x81]15 ; MCORE: mrs r1, xpsr @ encoding: [0xef,0xf3,0x03,0x81]16 ; MCORE: mrs r1, ipsr @ encoding: [0xef,0xf3,0x05,0x81]17 ; MCORE: mrs r1, epsr @ encoding: [0xef,0xf3,0x06,0x81]18 ; MCORE: mrs r1, iepsr @ encoding: [0xef,0xf3,0x07,0x81]19 ; MCORE: mrs r1, msp @ encoding: [0xef,0xf3,0x08,0x81]20 ; MCORE: mrs r1, psp @ encoding: [0xef,0xf3,0x09,0x81]21 ; MCORE: mrs r1, primask @ encoding: [0xef,0xf3,0x10,0x81]22 ; MCORE: mrs r1, basepri @ encoding: [0xef,0xf3,0x11,0x81]23 ; MCORE: mrs r1, basepri_max @ encoding: [0xef,0xf3,0x12,0x81]24 ; MCORE: mrs r1, faultmask @ encoding: [0xef,0xf3,0x13,0x81]25 ; MCORE: mrs r1, control @ encoding: [0xef,0xf3,0x14,0x81]26 27 %0 = call i32 @llvm.read_register.i32(metadata !0)28 %1 = call i32 @llvm.read_register.i32(metadata !4)29 %add1 = add i32 %1, %030 %2 = call i32 @llvm.read_register.i32(metadata !8)31 %add2 = add i32 %add1, %232 %3 = call i32 @llvm.read_register.i32(metadata !12)33 %add3 = add i32 %add2, %334 %4 = call i32 @llvm.read_register.i32(metadata !16)35 %add4 = add i32 %add3, %436 %5 = call i32 @llvm.read_register.i32(metadata !17)37 %add5 = add i32 %add4, %538 %6 = call i32 @llvm.read_register.i32(metadata !18)39 %add6 = add i32 %add5, %640 %7 = call i32 @llvm.read_register.i32(metadata !19)41 %add7 = add i32 %add6, %742 %8 = call i32 @llvm.read_register.i32(metadata !20)43 %add8 = add i32 %add7, %844 %9 = call i32 @llvm.read_register.i32(metadata !21)45 %add9 = add i32 %add8, %946 %10 = call i32 @llvm.read_register.i32(metadata !22)47 %add10 = add i32 %add9, %1048 %11 = call i32 @llvm.read_register.i32(metadata !23)49 %add11 = add i32 %add10, %1150 %12 = call i32 @llvm.read_register.i32(metadata !24)51 %add12 = add i32 %add11, %1252 %13 = call i32 @llvm.read_register.i32(metadata !25)53 %add13 = add i32 %add12, %1354 ret i32 %add1355}56 57define void @write_mclass_registers(i32 %x) nounwind {58entry:59 ; MCORE-LABEL: write_mclass_registers:60 ; MCORE: msr apsr_nzcvq, r0 @ encoding: [0x80,0xf3,0x00,0x88]61 ; MCORE: msr apsr_nzcvq, r0 @ encoding: [0x80,0xf3,0x00,0x88]62 ; MCORE: msr apsr_g, r0 @ encoding: [0x80,0xf3,0x00,0x84]63 ; MCORE: msr apsr_nzcvqg, r0 @ encoding: [0x80,0xf3,0x00,0x8c]64 ; MCORE: msr iapsr_nzcvq, r0 @ encoding: [0x80,0xf3,0x01,0x88]65 ; MCORE: msr iapsr_nzcvq, r0 @ encoding: [0x80,0xf3,0x01,0x88]66 ; MCORE: msr iapsr_g, r0 @ encoding: [0x80,0xf3,0x01,0x84]67 ; MCORE: msr iapsr_nzcvqg, r0 @ encoding: [0x80,0xf3,0x01,0x8c]68 ; MCORE: msr eapsr_nzcvq, r0 @ encoding: [0x80,0xf3,0x02,0x88]69 ; MCORE: msr eapsr_nzcvq, r0 @ encoding: [0x80,0xf3,0x02,0x88]70 ; MCORE: msr eapsr_g, r0 @ encoding: [0x80,0xf3,0x02,0x84]71 ; MCORE: msr eapsr_nzcvqg, r0 @ encoding: [0x80,0xf3,0x02,0x8c]72 ; MCORE: msr xpsr_nzcvq, r0 @ encoding: [0x80,0xf3,0x03,0x88]73 ; MCORE: msr xpsr_nzcvq, r0 @ encoding: [0x80,0xf3,0x03,0x88]74 ; MCORE: msr xpsr_g, r0 @ encoding: [0x80,0xf3,0x03,0x84]75 ; MCORE: msr xpsr_nzcvqg, r0 @ encoding: [0x80,0xf3,0x03,0x8c]76 ; MCORE: msr ipsr, r0 @ encoding: [0x80,0xf3,0x05,0x88]77 ; MCORE: msr epsr, r0 @ encoding: [0x80,0xf3,0x06,0x88]78 ; MCORE: msr iepsr, r0 @ encoding: [0x80,0xf3,0x07,0x88]79 ; MCORE: msr msp, r0 @ encoding: [0x80,0xf3,0x08,0x88]80 ; MCORE: msr psp, r0 @ encoding: [0x80,0xf3,0x09,0x88]81 ; MCORE: msr primask, r0 @ encoding: [0x80,0xf3,0x10,0x88]82 ; MCORE: msr basepri, r0 @ encoding: [0x80,0xf3,0x11,0x88]83 ; MCORE: msr basepri_max, r0 @ encoding: [0x80,0xf3,0x12,0x88]84 ; MCORE: msr faultmask, r0 @ encoding: [0x80,0xf3,0x13,0x88]85 ; MCORE: msr control, r0 @ encoding: [0x80,0xf3,0x14,0x88]86 87 call void @llvm.write_register.i32(metadata !0, i32 %x)88 call void @llvm.write_register.i32(metadata !1, i32 %x)89 call void @llvm.write_register.i32(metadata !2, i32 %x)90 call void @llvm.write_register.i32(metadata !3, i32 %x)91 call void @llvm.write_register.i32(metadata !4, i32 %x)92 call void @llvm.write_register.i32(metadata !5, i32 %x)93 call void @llvm.write_register.i32(metadata !6, i32 %x)94 call void @llvm.write_register.i32(metadata !7, i32 %x)95 call void @llvm.write_register.i32(metadata !8, i32 %x)96 call void @llvm.write_register.i32(metadata !9, i32 %x)97 call void @llvm.write_register.i32(metadata !10, i32 %x)98 call void @llvm.write_register.i32(metadata !11, i32 %x)99 call void @llvm.write_register.i32(metadata !12, i32 %x)100 call void @llvm.write_register.i32(metadata !13, i32 %x)101 call void @llvm.write_register.i32(metadata !14, i32 %x)102 call void @llvm.write_register.i32(metadata !15, i32 %x)103 call void @llvm.write_register.i32(metadata !16, i32 %x)104 call void @llvm.write_register.i32(metadata !17, i32 %x)105 call void @llvm.write_register.i32(metadata !18, i32 %x)106 call void @llvm.write_register.i32(metadata !19, i32 %x)107 call void @llvm.write_register.i32(metadata !20, i32 %x)108 call void @llvm.write_register.i32(metadata !21, i32 %x)109 call void @llvm.write_register.i32(metadata !22, i32 %x)110 call void @llvm.write_register.i32(metadata !23, i32 %x)111 call void @llvm.write_register.i32(metadata !24, i32 %x)112 call void @llvm.write_register.i32(metadata !25, i32 %x)113 ret void114}115 116declare i32 @llvm.read_register.i32(metadata) nounwind117declare void @llvm.write_register.i32(metadata, i32) nounwind118 119!0 = !{!"apsr"}120!1 = !{!"apsr_nzcvq"}121!2 = !{!"apsr_g"}122!3 = !{!"apsr_nzcvqg"}123!4 = !{!"iapsr"}124!5 = !{!"iapsr_nzcvq"}125!6 = !{!"iapsr_g"}126!7 = !{!"iapsr_nzcvqg"}127!8 = !{!"eapsr"}128!9 = !{!"eapsr_nzcvq"}129!10 = !{!"eapsr_g"}130!11 = !{!"eapsr_nzcvqg"}131!12 = !{!"xpsr"}132!13 = !{!"xpsr_nzcvq"}133!14 = !{!"xpsr_g"}134!15 = !{!"xpsr_nzcvqg"}135!16 = !{!"ipsr"}136!17 = !{!"epsr"}137!18 = !{!"iepsr"}138!19 = !{!"msp"}139!20 = !{!"psp"}140!21 = !{!"primask"}141!22 = !{!"basepri"}142!23 = !{!"basepri_max"}143!24 = !{!"faultmask"}144!25 = !{!"control"}145