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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc < %s -mtriple=arm-none-eabi -mcpu=cortex-a8 2>&1 | FileCheck %s --check-prefix=ARM --check-prefix=ACORE3; RUN: llc < %s -mtriple=thumb-none-eabi -mcpu=cortex-m4 2>&1 | FileCheck %s --check-prefix=ARM --check-prefix=MCORE4 5define i32 @read_i32_encoded_register() nounwind {6; ARM-LABEL: read_i32_encoded_register:7; ARM: @ %bb.0: @ %entry8; ARM-NEXT: mrc p1, #2, r0, c3, c4, #59; ARM-NEXT: bx lr10entry:11 %reg = call i32 @llvm.read_register.i32(metadata !0)12 ret i32 %reg13}14 15define i64 @read_i64_encoded_register() nounwind {16; ARM-LABEL: read_i64_encoded_register:17; ARM: @ %bb.0: @ %entry18; ARM-NEXT: mrrc p1, #2, r0, r1, c319; ARM-NEXT: bx lr20entry:21 %reg = call i64 @llvm.read_register.i64(metadata !1)22 ret i64 %reg23}24 25define i64 @read_volatile_i64_twice() {26; ACORE-LABEL: read_volatile_i64_twice:27; ACORE: @ %bb.0: @ %entry28; ACORE-NEXT: mrrc p15, #1, r0, r1, c1429; ACORE-NEXT: mrrc p15, #1, r2, r3, c1430; ACORE-NEXT: eor r0, r2, r031; ACORE-NEXT: eor r1, r3, r132; ACORE-NEXT: bx lr33;34; MCORE-LABEL: read_volatile_i64_twice:35; MCORE: @ %bb.0: @ %entry36; MCORE-NEXT: mrrc p15, #1, r0, r1, c1437; MCORE-NEXT: mrrc p15, #1, r2, r3, c1438; MCORE-NEXT: eors r0, r239; MCORE-NEXT: eors r1, r340; MCORE-NEXT: bx lr41entry:42 %0 = tail call i64 @llvm.read_volatile_register.i64(metadata !5)43 %1 = tail call i64 @llvm.read_volatile_register.i64(metadata !5)44 %xor = xor i64 %1, %045 ret i64 %xor46}47 48 49define i32 @read_apsr() nounwind {50; ARM-LABEL: read_apsr:51; ARM: @ %bb.0: @ %entry52; ARM-NEXT: mrs r0, apsr53; ARM-NEXT: bx lr54entry:55 %reg = call i32 @llvm.read_register.i32(metadata !2)56 ret i32 %reg57}58 59define i32 @read_fpscr() nounwind {60; ARM-LABEL: read_fpscr:61; ARM: @ %bb.0: @ %entry62; ARM-NEXT: vmrs r0, fpscr63; ARM-NEXT: bx lr64entry:65 %reg = call i32 @llvm.read_register.i32(metadata !3)66 ret i32 %reg67}68 69define void @write_i32_encoded_register(i32 %x) nounwind {70; ARM-LABEL: write_i32_encoded_register:71; ARM: @ %bb.0: @ %entry72; ARM-NEXT: mcr p1, #2, r0, c3, c4, #573; ARM-NEXT: bx lr74entry:75 call void @llvm.write_register.i32(metadata !0, i32 %x)76 ret void77}78 79define void @write_i64_encoded_register(i64 %x) nounwind {80; ARM-LABEL: write_i64_encoded_register:81; ARM: @ %bb.0: @ %entry82; ARM-NEXT: mcrr p1, #2, r0, r1, c383; ARM-NEXT: bx lr84entry:85 call void @llvm.write_register.i64(metadata !1, i64 %x)86 ret void87}88 89define void @write_apsr(i32 %x) nounwind {90; ACORE-LABEL: write_apsr:91; ACORE: @ %bb.0: @ %entry92; ACORE-NEXT: msr APSR_nzcvq, r093; ACORE-NEXT: bx lr94;95; MCORE-LABEL: write_apsr:96; MCORE: @ %bb.0: @ %entry97; MCORE-NEXT: msr apsr_nzcvq, r098; MCORE-NEXT: bx lr99entry:100 call void @llvm.write_register.i32(metadata !4, i32 %x)101 ret void102}103 104define void @write_fpscr(i32 %x) nounwind {105; ARM-LABEL: write_fpscr:106; ARM: @ %bb.0: @ %entry107; ARM-NEXT: vmsr fpscr, r0108; ARM-NEXT: bx lr109entry:110 call void @llvm.write_register.i32(metadata !3, i32 %x)111 ret void112}113 114declare i32 @llvm.read_register.i32(metadata) nounwind115declare i64 @llvm.read_register.i64(metadata) nounwind116declare void @llvm.write_register.i32(metadata, i32) nounwind117declare void @llvm.write_register.i64(metadata, i64) nounwind118 119!0 = !{!"cp1:2:c3:c4:5"}120!1 = !{!"cp1:2:c3"}121!2 = !{!"apsr"}122!3 = !{!"fpscr"}123!4 = !{!"apsr_nzcvq"}124!5 = !{!"cp15:1:c14"}125