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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=armv6-eabi %s -o - | FileCheck %s 3; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+dsp %s -o - | FileCheck %s4 5define arm_aapcs_vfpcc i32 @ssat_lsl(i32 %num){6; CHECK-LABEL: ssat_lsl7; CHECK: @ %bb.0: @ %entry8; CHECK-NEXT: ssat r0, #8, r0, lsl #79; CHECK-NEXT: bx lr10entry:11 %shl = shl i32 %num, 712 %0 = tail call i32 @llvm.arm.ssat(i32 %shl, i32 8)13 ret i32 %014}15 16define arm_aapcs_vfpcc i32 @ssat_asr(i32 %num){17; CHECK-LABEL: ssat_asr18; CHECK: @ %bb.0: @ %entry19; CHECK-NEXT: ssat r0, #8, r0, asr #720; CHECK-NEXT: bx lr21entry:22 %shr = ashr i32 %num, 723 %0 = tail call i32 @llvm.arm.ssat(i32 %shr, i32 8)24 ret i32 %025}26 27define arm_aapcs_vfpcc i32 @ssat_lsl2(i32 %num){28; CHECK-LABEL: ssat_lsl2:29; CHECK: @ %bb.0: @ %entry30; CHECK-NEXT: ssat r0, #16, r0, lsl #1531; CHECK-NEXT: bx lr32entry:33 %shl = shl nsw i32 %num, 1534 %0 = icmp sgt i32 %shl, -3276835 %1 = select i1 %0, i32 %shl, i32 -3276836 %2 = icmp slt i32 %1, 3276737 %3 = select i1 %2, i32 %1, i32 3276738 ret i32 %339}40 41define arm_aapcs_vfpcc i32 @ssat_asr2(i32 %num){42; CHECK-LABEL: ssat_asr2:43; CHECK: @ %bb.0: @ %entry44; CHECK-NEXT: ssat r0, #16, r0, asr #1545; CHECK-NEXT: bx lr46entry:47 %shr = ashr i32 %num, 1548 %0 = icmp sgt i32 %shr, -3276849 %1 = select i1 %0, i32 %shr, i32 -3276850 %2 = icmp slt i32 %1, 3276751 %3 = select i1 %2, i32 %1, i32 3276752 ret i32 %353}54 55declare i32 @llvm.arm.ssat(i32, i32)56