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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 62; RUN: llc -mtriple armv7-- -mattr=+vfp4 -O0 -o - %s | FileCheck %s3; RUN: llc -mtriple armv7-- -mattr=+vfp4 -O3 -o - %s | FileCheck %s --check-prefix=CHECK-O34 5declare float @llvm.experimental.constrained.sitofp.f32.i32(i32, metadata, metadata)6declare float @llvm.experimental.constrained.sitofp.f32.i16(i16, metadata, metadata)7declare i1 @llvm.experimental.constrained.fcmp.f32(float, float, metadata, metadata)8declare float @llvm.experimental.constrained.uitofp.f32.i16(i16, metadata, metadata)9 10define i32 @test(i32 %a, i16 %b) #0 {11; CHECK-LABEL: test:12; CHECK: @ %bb.0: @ %entry13; CHECK-NEXT: sub sp, sp, #1614; CHECK-NEXT: mov r2, r015; CHECK-NEXT: sxth r0, r116; CHECK-NEXT: movw r1, #017; CHECK-NEXT: movt r1, #1720018; CHECK-NEXT: str r1, [sp, #4]19; CHECK-NEXT: eor r2, r2, #-214748364820; CHECK-NEXT: str r2, [sp]21; CHECK-NEXT: vldr d16, [sp]22; CHECK-NEXT: vldr d17, .LCPI0_023; CHECK-NEXT: vsub.f64 d16, d16, d1724; CHECK-NEXT: vcvt.f32.f64 s0, d1625; CHECK-NEXT: str r1, [sp, #12]26; CHECK-NEXT: eor r0, r0, #-214748364827; CHECK-NEXT: str r0, [sp, #8]28; CHECK-NEXT: vldr d16, [sp, #8]29; CHECK-NEXT: vsub.f64 d16, d16, d1730; CHECK-NEXT: vcvt.f32.f64 s2, d1631; CHECK-NEXT: vcmp.f32 s0, s232; CHECK-NEXT: vmrs APSR_nzcv, fpscr33; CHECK-NEXT: mov r0, #034; CHECK-NEXT: movweq r0, #135; CHECK-NEXT: add sp, sp, #1636; CHECK-NEXT: bx lr37; CHECK-NEXT: .p2align 338; CHECK-NEXT: @ %bb.1:39; CHECK-NEXT: .LCPI0_0:40; CHECK-NEXT: .long 2147483648 @ double 450360177485414441; CHECK-NEXT: .long 112721920042;43; CHECK-O3-LABEL: test:44; CHECK-O3: @ %bb.0: @ %entry45; CHECK-O3-NEXT: sub sp, sp, #1646; CHECK-O3-NEXT: sxth r1, r147; CHECK-O3-NEXT: movw r2, #048; CHECK-O3-NEXT: movt r2, #1720049; CHECK-O3-NEXT: str r2, [sp, #4]50; CHECK-O3-NEXT: eor r0, r0, #-214748364851; CHECK-O3-NEXT: str r0, [sp]52; CHECK-O3-NEXT: vldr d16, [sp]53; CHECK-O3-NEXT: vldr d17, .LCPI0_054; CHECK-O3-NEXT: vsub.f64 d16, d16, d1755; CHECK-O3-NEXT: vcvt.f32.f64 s0, d1656; CHECK-O3-NEXT: str r2, [sp, #12]57; CHECK-O3-NEXT: eor r0, r1, #-214748364858; CHECK-O3-NEXT: str r0, [sp, #8]59; CHECK-O3-NEXT: vldr d16, [sp, #8]60; CHECK-O3-NEXT: vsub.f64 d16, d16, d1761; CHECK-O3-NEXT: vcvt.f32.f64 s2, d1662; CHECK-O3-NEXT: vcmp.f32 s0, s263; CHECK-O3-NEXT: vmrs APSR_nzcv, fpscr64; CHECK-O3-NEXT: mov r0, #065; CHECK-O3-NEXT: movweq r0, #166; CHECK-O3-NEXT: add sp, sp, #1667; CHECK-O3-NEXT: bx lr68; CHECK-O3-NEXT: .p2align 369; CHECK-O3-NEXT: @ %bb.1:70; CHECK-O3-NEXT: .LCPI0_0:71; CHECK-O3-NEXT: .long 2147483648 @ double 450360177485414472; CHECK-O3-NEXT: .long 112721920073entry:74 %conv = call float @llvm.experimental.constrained.sitofp.f32.i32(i32 %a, metadata !"round.tonearest", metadata !"fpexcept.strict") #175 %conv1 = call float @llvm.experimental.constrained.sitofp.f32.i16(i16 %b, metadata !"round.tonearest", metadata !"fpexcept.strict") #176 %cmp = call i1 @llvm.experimental.constrained.fcmp.f32(float %conv, float %conv1, metadata !"oeq", metadata !"fpexcept.strict") #177 %conv2 = zext i1 %cmp to i3278 ret i32 %conv279}80 81define i32 @test2(i32 %a, i16 %b) #0 {82; CHECK-LABEL: test2:83; CHECK: @ %bb.0: @ %entry84; CHECK-NEXT: sub sp, sp, #1685; CHECK-NEXT: mov r2, r086; CHECK-NEXT: uxth r0, r187; CHECK-NEXT: movw r1, #088; CHECK-NEXT: movt r1, #1720089; CHECK-NEXT: str r1, [sp, #4]90; CHECK-NEXT: eor r2, r2, #-214748364891; CHECK-NEXT: str r2, [sp]92; CHECK-NEXT: vldr d16, [sp]93; CHECK-NEXT: vldr d17, .LCPI1_094; CHECK-NEXT: vsub.f64 d16, d16, d1795; CHECK-NEXT: vcvt.f32.f64 s0, d1696; CHECK-NEXT: str r1, [sp, #12]97; CHECK-NEXT: str r0, [sp, #8]98; CHECK-NEXT: vldr d16, [sp, #8]99; CHECK-NEXT: vldr d17, .LCPI1_1100; CHECK-NEXT: vsub.f64 d16, d16, d17101; CHECK-NEXT: vcvt.f32.f64 s2, d16102; CHECK-NEXT: vcmp.f32 s0, s2103; CHECK-NEXT: vmrs APSR_nzcv, fpscr104; CHECK-NEXT: mov r0, #0105; CHECK-NEXT: movweq r0, #1106; CHECK-NEXT: add sp, sp, #16107; CHECK-NEXT: bx lr108; CHECK-NEXT: .p2align 3109; CHECK-NEXT: @ %bb.1:110; CHECK-NEXT: .LCPI1_0:111; CHECK-NEXT: .long 2147483648 @ double 4503601774854144112; CHECK-NEXT: .long 1127219200113; CHECK-NEXT: .LCPI1_1:114; CHECK-NEXT: .long 0 @ double 4503599627370496115; CHECK-NEXT: .long 1127219200116;117; CHECK-O3-LABEL: test2:118; CHECK-O3: @ %bb.0: @ %entry119; CHECK-O3-NEXT: sub sp, sp, #16120; CHECK-O3-NEXT: uxth r1, r1121; CHECK-O3-NEXT: movw r2, #0122; CHECK-O3-NEXT: movt r2, #17200123; CHECK-O3-NEXT: str r2, [sp, #4]124; CHECK-O3-NEXT: eor r0, r0, #-2147483648125; CHECK-O3-NEXT: str r0, [sp]126; CHECK-O3-NEXT: vldr d16, [sp]127; CHECK-O3-NEXT: vldr d17, .LCPI1_0128; CHECK-O3-NEXT: vsub.f64 d16, d16, d17129; CHECK-O3-NEXT: vcvt.f32.f64 s0, d16130; CHECK-O3-NEXT: str r2, [sp, #12]131; CHECK-O3-NEXT: str r1, [sp, #8]132; CHECK-O3-NEXT: vldr d16, [sp, #8]133; CHECK-O3-NEXT: vldr d17, .LCPI1_1134; CHECK-O3-NEXT: vsub.f64 d16, d16, d17135; CHECK-O3-NEXT: vcvt.f32.f64 s2, d16136; CHECK-O3-NEXT: vcmp.f32 s0, s2137; CHECK-O3-NEXT: vmrs APSR_nzcv, fpscr138; CHECK-O3-NEXT: mov r0, #0139; CHECK-O3-NEXT: movweq r0, #1140; CHECK-O3-NEXT: add sp, sp, #16141; CHECK-O3-NEXT: bx lr142; CHECK-O3-NEXT: .p2align 3143; CHECK-O3-NEXT: @ %bb.1:144; CHECK-O3-NEXT: .LCPI1_0:145; CHECK-O3-NEXT: .long 2147483648 @ double 4503601774854144146; CHECK-O3-NEXT: .long 1127219200147; CHECK-O3-NEXT: .LCPI1_1:148; CHECK-O3-NEXT: .long 0 @ double 4503599627370496149; CHECK-O3-NEXT: .long 1127219200150entry:151 %conv = call float @llvm.experimental.constrained.sitofp.f32.i32(i32 %a, metadata !"round.tonearest", metadata !"fpexcept.strict") #1152 %conv1 = call float @llvm.experimental.constrained.uitofp.f32.i16(i16 %b, metadata !"round.tonearest", metadata !"fpexcept.strict") #1153 %cmp = call i1 @llvm.experimental.constrained.fcmp.f32(float %conv, float %conv1, metadata !"oeq", metadata !"fpexcept.strict") #1154 %conv2 = zext i1 %cmp to i32155 ret i32 %conv2156}157 158attributes #0 = { strictfp noinline optnone }159attributes #1 = { strictfp }160