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1; RUN: llc -mtriple=armv7-apple-ios6.0 -mcpu=swift < %s | FileCheck %s2; RUN: llc -mtriple=armv7-apple-ios6.0 < %s | FileCheck %s --check-prefix=CHECK-STRICT-ATOMIC3 4; Release operations only need the store barrier provided by a "dmb ishst",5 6define void @test_store_release(ptr %p, i32 %v) {7; CHECK-LABEL: test_store_release:8; CHECK: dmb ishst9; CHECK: str10 11; CHECK-STRICT-ATOMIC-LABEL: test_store_release:12; CHECK-STRICT-ATOMIC: dmb {{ish$}}13 store atomic i32 %v, ptr %p release, align 414 ret void15}16 17; However, if sequential consistency is needed *something* must ensure a release18; followed by an acquire does not get reordered. In that case a "dmb ishst" is19; not adequate.20define i32 @test_seq_cst(ptr %p, i32 %v) {21; CHECK-LABEL: test_seq_cst:22; CHECK: dmb ishst23; CHECK: str24; CHECK: dmb {{ish$}}25; CHECK: ldr26; CHECK: dmb {{ish$}}27 28; CHECK-STRICT-ATOMIC-LABEL: test_seq_cst:29; CHECK-STRICT-ATOMIC: dmb {{ish$}}30; CHECK-STRICT-ATOMIC: str31; CHECK-STRICT-ATOMIC: dmb {{ish$}}32; CHECK-STRICT-ATOMIC: ldr33; CHECK-STRICT-ATOMIC: dmb {{ish$}}34 35 store atomic i32 %v, ptr %p seq_cst, align 436 %val = load atomic i32, ptr %p seq_cst, align 437 ret i32 %val38}39 40; Also, pure acquire operations should definitely not have an ishst barrier.41 42define i32 @test_acq(ptr %addr) {43; CHECK-LABEL: test_acq:44; CHECK: ldr45; CHECK: dmb {{ish$}}46 47; CHECK-STRICT-ATOMIC-LABEL: test_acq:48; CHECK-STRICT-ATOMIC: dmb {{ish$}}49 %val = load atomic i32, ptr %addr acquire, align 450 ret i32 %val51}52