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1; RUN: llc -mtriple=armv7k-apple-ios8.0 -mcpu=cortex-a7 -verify-machineinstrs < %s | FileCheck %s2; RUN: llc -mtriple=armv7k-apple-ios8.0 -mcpu=cortex-a7 -verify-machineinstrs < %s -O0 | FileCheck --check-prefix=CHECK-O0 %s3 4; RUN: llc -mtriple=armv7-apple-ios -verify-machineinstrs < %s | FileCheck %s5; RUN: llc -mtriple=armv7-apple-ios -verify-machineinstrs < %s -O0 | FileCheck --check-prefix=CHECK-O0 %s6 7; Test how llvm handles return type of {i16, i8}. The return value will be8; passed in %r0 and %r1.9; CHECK-LABEL: test:10; CHECK: bl {{.*}}gen11; CHECK: sxth {{.*}}, r012; CHECK: sxtab r0, {{.*}}, r113; CHECK-O0-LABEL: test:14; CHECK-O0: bl {{.*}}gen15; CHECK-O0: sxth r0, r016; CHECK-O0: sxtb r1, r117; CHECK-O0: add r0, r0, r118define i16 @test(i32 %key) {19entry:20 %key.addr = alloca i32, align 421 store i32 %key, ptr %key.addr, align 422 %0 = load i32, ptr %key.addr, align 423 %call = call swiftcc { i16, i8 } @gen(i32 %0)24 %v3 = extractvalue { i16, i8 } %call, 025 %v1 = sext i16 %v3 to i3226 %v5 = extractvalue { i16, i8 } %call, 127 %v2 = sext i8 %v5 to i3228 %add = add nsw i32 %v1, %v229 %conv = trunc i32 %add to i1630 ret i16 %conv31}32 33declare swiftcc { i16, i8 } @gen(i32)34 35; We can't pass every return value in register, instead, pass everything in36; memroy.37; The caller provides space for the return value and passes the address in %r0.38; The first input argument will be in %r1.39; CHECK-LABEL: test2:40; CHECK: mov r1, r041; CHECK: mov r0, sp42; CHECK: bl {{.*}}gen243; CHECK-DAG: add44; CHECK-DAG: ldr {{.*}}, [sp, #16]45; CHECK-DAG: add46; CHECK-DAG: add47; CHECK-DAG: add48; CHECK-O0-LABEL: test2:49; CHECK-O0: str r050; CHECK-O0: mov r0, sp51; CHECK-O0: bl {{.*}}gen252; CHECK-O0-DAG: ldr {{.*}}, [sp]53; CHECK-O0-DAG: ldr {{.*}}, [sp, #4]54; CHECK-O0-DAG: ldr {{.*}}, [sp, #8]55; CHECK-O0-DAG: ldr {{.*}}, [sp, #12]56; CHECK-O0-DAG: ldr {{.*}}, [sp, #16]57; CHECK-O0-DAG: add58; CHECK-O0-DAG: add59; CHECK-O0-DAG: add60; CHECK-O0-DAG: add61define i32 @test2(i32 %key) #0 {62entry:63 %key.addr = alloca i32, align 464 store i32 %key, ptr %key.addr, align 465 %0 = load i32, ptr %key.addr, align 466 %call = call swiftcc { i32, i32, i32, i32, i32 } @gen2(i32 %0)67 68 %v3 = extractvalue { i32, i32, i32, i32, i32 } %call, 069 %v5 = extractvalue { i32, i32, i32, i32, i32 } %call, 170 %v6 = extractvalue { i32, i32, i32, i32, i32 } %call, 271 %v7 = extractvalue { i32, i32, i32, i32, i32 } %call, 372 %v8 = extractvalue { i32, i32, i32, i32, i32 } %call, 473 74 %add = add nsw i32 %v3, %v575 %add1 = add nsw i32 %add, %v676 %add2 = add nsw i32 %add1, %v777 %add3 = add nsw i32 %add2, %v878 ret i32 %add379}80 81; The address of the return value is passed in %r0.82; CHECK-LABEL: gen2:83; CHECK-DAG: str r1, [r0]84; CHECK-DAG: str r1, [r0, #4]85; CHECK-DAG: str r1, [r0, #8]86; CHECK-DAG: str r1, [r0, #12]87; CHECK-DAG: str r1, [r0, #16]88; CHECK-O0-LABEL: gen2:89; CHECK-O0-DAG: str r1, [r0]90; CHECK-O0-DAG: str r1, [r0, #4]91; CHECK-O0-DAG: str r1, [r0, #8]92; CHECK-O0-DAG: str r1, [r0, #12]93; CHECK-O0-DAG: str r1, [r0, #16]94define swiftcc { i32, i32, i32, i32, i32 } @gen2(i32 %key) {95 %Y = insertvalue { i32, i32, i32, i32, i32 } undef, i32 %key, 096 %Z = insertvalue { i32, i32, i32, i32, i32 } %Y, i32 %key, 197 %Z2 = insertvalue { i32, i32, i32, i32, i32 } %Z, i32 %key, 298 %Z3 = insertvalue { i32, i32, i32, i32, i32 } %Z2, i32 %key, 399 %Z4 = insertvalue { i32, i32, i32, i32, i32 } %Z3, i32 %key, 4100 ret { i32, i32, i32, i32, i32 } %Z4101}102 103; The return value {i32, i32, i32, i32} will be returned via registers %r0, %r1,104; %r2, %r3.105; CHECK-LABEL: test3:106; CHECK: bl {{.*}}gen3107; CHECK: add r0, r0, r1108; CHECK: add r0, r0, r2109; CHECK: add r0, r0, r3110; CHECK-O0-LABEL: test3:111; CHECK-O0: bl {{.*}}gen3112; CHECK-O0: add r0, r0, r1113; CHECK-O0: add r0, r0, r2114; CHECK-O0: add r0, r0, r3115define i32 @test3(i32 %key) #0 {116entry:117 %key.addr = alloca i32, align 4118 store i32 %key, ptr %key.addr, align 4119 %0 = load i32, ptr %key.addr, align 4120 %call = call swiftcc { i32, i32, i32, i32 } @gen3(i32 %0)121 122 %v3 = extractvalue { i32, i32, i32, i32 } %call, 0123 %v5 = extractvalue { i32, i32, i32, i32 } %call, 1124 %v6 = extractvalue { i32, i32, i32, i32 } %call, 2125 %v7 = extractvalue { i32, i32, i32, i32 } %call, 3126 127 %add = add nsw i32 %v3, %v5128 %add1 = add nsw i32 %add, %v6129 %add2 = add nsw i32 %add1, %v7130 ret i32 %add2131}132 133declare swiftcc { i32, i32, i32, i32 } @gen3(i32 %key)134 135; The return value {float, float, float, float} will be returned via registers136; s0-s3.137; CHECK-LABEL: test4:138; CHECK: bl _gen4139; CHECK: vadd.f32 s0, s0, s1140; CHECK: vadd.f32 s0, s0, s2141; CHECK: vadd.f32 s0, s0, s3142; CHECK-O0-LABEL: test4:143; CHECK-O0: bl _gen4144; CHECK-O0: vadd.f32 s0, s0, s1145; CHECK-O0: vadd.f32 s0, s0, s2146; CHECK-O0: vadd.f32 s0, s0, s3147define float @test4(float %key) #0 {148entry:149 %key.addr = alloca float, align 4150 store float %key, ptr %key.addr, align 4151 %0 = load float, ptr %key.addr, align 4152 %call = call swiftcc { float, float, float, float } @gen4(float %0)153 154 %v3 = extractvalue { float, float, float, float } %call, 0155 %v5 = extractvalue { float, float, float, float } %call, 1156 %v6 = extractvalue { float, float, float, float } %call, 2157 %v7 = extractvalue { float, float, float, float } %call, 3158 159 %add = fadd float %v3, %v5160 %add1 = fadd float %add, %v6161 %add2 = fadd float %add1, %v7162 ret float %add2163}164 165declare swiftcc { float, float, float, float } @gen4(float %key)166 167; CHECK-LABEL: test5168; CHECK: bl _gen5169; CHECK: vadd.f64 [[TMP:d.*]], d0, d1170; CHECK: vadd.f64 [[TMP]], [[TMP]], d2171; CHECK: vadd.f64 d0, [[TMP]], d3172define swiftcc double @test5() #0 {173entry:174 %call = call swiftcc { double, double, double, double } @gen5()175 176 %v3 = extractvalue { double, double, double, double } %call, 0177 %v5 = extractvalue { double, double, double, double } %call, 1178 %v6 = extractvalue { double, double, double, double } %call, 2179 %v7 = extractvalue { double, double, double, double } %call, 3180 181 %add = fadd double %v3, %v5182 %add1 = fadd double %add, %v6183 %add2 = fadd double %add1, %v7184 ret double %add2185}186 187declare swiftcc { double, double, double, double } @gen5()188 189 190; CHECK-LABEL: test6191; CHECK: bl _gen6192; CHECK-DAG: vadd.f64 [[TMP:d.*]], d0, d1193; CHECK-DAG: add r0, r0, r1194; CHECK-DAG: add r0, r0, r2195; CHECK-DAG: add r0, r0, r3196; CHECK-DAG: vadd.f64 [[TMP]], [[TMP]], d2197; CHECK-DAG: vadd.f64 d0, [[TMP]], d3198define swiftcc { double, i32 } @test6() #0 {199entry:200 %call = call swiftcc { double, double, double, double, i32, i32, i32, i32 } @gen6()201 202 %v3 = extractvalue { double, double, double, double, i32, i32, i32, i32 } %call, 0203 %v5 = extractvalue { double, double, double, double, i32, i32, i32, i32 } %call, 1204 %v6 = extractvalue { double, double, double, double, i32, i32, i32, i32 } %call, 2205 %v7 = extractvalue { double, double, double, double, i32, i32, i32, i32 } %call, 3206 %v3.i = extractvalue { double, double, double, double, i32, i32, i32, i32 } %call, 4207 %v5.i = extractvalue { double, double, double, double, i32, i32, i32, i32 } %call, 5208 %v6.i = extractvalue { double, double, double, double, i32, i32, i32, i32 } %call, 6209 %v7.i = extractvalue { double, double, double, double, i32, i32, i32, i32 } %call, 7210 211 %add = fadd double %v3, %v5212 %add1 = fadd double %add, %v6213 %add2 = fadd double %add1, %v7214 215 %add.i = add nsw i32 %v3.i, %v5.i216 %add1.i = add nsw i32 %add.i, %v6.i217 %add2.i = add nsw i32 %add1.i, %v7.i218 219 %Y = insertvalue { double, i32 } undef, double %add2, 0220 %Z = insertvalue { double, i32 } %Y, i32 %add2.i, 1221 ret { double, i32} %Z222}223 224declare swiftcc { double, double, double, double, i32, i32, i32, i32 } @gen6()225 226; CHECK-LABEL: gen7227; CHECK: mov r1, r0228; CHECK: mov r2, r0229; CHECK: mov r3, r0230; CHECK: bx lr231define swiftcc { i32, i32, i32, i32 } @gen7(i32 %key) {232 %v0 = insertvalue { i32, i32, i32, i32 } undef, i32 %key, 0233 %v1 = insertvalue { i32, i32, i32, i32 } %v0, i32 %key, 1234 %v2 = insertvalue { i32, i32, i32, i32 } %v1, i32 %key, 2235 %v3 = insertvalue { i32, i32, i32, i32 } %v2, i32 %key, 3236 ret { i32, i32, i32, i32 } %v3237}238 239; CHECK-LABEL: gen9240; CHECK: mov r1, r0241; CHECK: mov r2, r0242; CHECK: mov r3, r0243; CHECK: bx lr244define swiftcc { i8, i8, i8, i8 } @gen9(i8 %key) {245 %v0 = insertvalue { i8, i8, i8, i8 } undef, i8 %key, 0246 %v1 = insertvalue { i8, i8, i8, i8 } %v0, i8 %key, 1247 %v2 = insertvalue { i8, i8, i8, i8 } %v1, i8 %key, 2248 %v3 = insertvalue { i8, i8, i8, i8 } %v2, i8 %key, 3249 ret { i8, i8, i8, i8 } %v3250}251; CHECK-LABEL: gen10252; CHECK-DAG: vmov.f64 d1, d0253; CHECK-DAG: mov r1, r0254; CHECK-DAG: mov r2, r0255; CHECK-DAG: mov r3, r0256; CHECK-DAG: vmov.f64 d2, d0257; CHECK-DAG: vmov.f64 d3, d0258; CHECK-DAG: bx lr259define swiftcc { double, double, double, double, i32, i32, i32, i32 } @gen10(double %keyd, i32 %keyi) {260 %v0 = insertvalue { double, double, double, double, i32, i32, i32, i32 } undef, double %keyd, 0261 %v1 = insertvalue { double, double, double, double, i32, i32, i32, i32 } %v0, double %keyd, 1262 %v2 = insertvalue { double, double, double, double, i32, i32, i32, i32 } %v1, double %keyd, 2263 %v3 = insertvalue { double, double, double, double, i32, i32, i32, i32 } %v2, double %keyd, 3264 %v4 = insertvalue { double, double, double, double, i32, i32, i32, i32 } %v3, i32 %keyi, 4265 %v5 = insertvalue { double, double, double, double, i32, i32, i32, i32 } %v4, i32 %keyi, 5266 %v6 = insertvalue { double, double, double, double, i32, i32, i32, i32 } %v5, i32 %keyi, 6267 %v7 = insertvalue { double, double, double, double, i32, i32, i32, i32 } %v6, i32 %keyi, 7268 ret { double, double, double, double, i32, i32, i32, i32 } %v7269}270 271 272; CHECK-LABEL: test11273; CHECK: bl _gen11274; CHECK: vadd.f32 [[TMP:q.*]], q0, q1275; CHECK: vadd.f32 [[TMP]], [[TMP]], q2276; CHECK: vadd.f32 q0, [[TMP]], q3277define swiftcc <4 x float> @test11() #0 {278entry:279 %call = call swiftcc { <4 x float>, <4 x float>, <4 x float>, <4 x float> } @gen11()280 281 %v3 = extractvalue { <4 x float>, <4 x float>, <4 x float>, <4 x float> } %call, 0282 %v5 = extractvalue { <4 x float>, <4 x float>, <4 x float>, <4 x float> } %call, 1283 %v6 = extractvalue { <4 x float>, <4 x float>, <4 x float>, <4 x float> } %call, 2284 %v7 = extractvalue { <4 x float>, <4 x float>, <4 x float>, <4 x float> } %call, 3285 286 %add = fadd <4 x float> %v3, %v5287 %add1 = fadd <4 x float> %add, %v6288 %add2 = fadd <4 x float> %add1, %v7289 ret <4 x float> %add2290}291 292declare swiftcc { <4 x float>, <4 x float>, <4 x float>, <4 x float> } @gen11()293 294; CHECK-LABEL: test12295; CHECK-DAG: vadd.f32 [[TMP:q.*]], q0, q1296; CHECK-DAG: vmov.f32 s4, s12297; CHECK-DAG: vadd.f32 q0, [[TMP]], q2298define swiftcc { <4 x float>, float } @test12() #0 {299entry:300 %call = call swiftcc { <4 x float>, <4 x float>, <4 x float>, float } @gen12()301 302 %v3 = extractvalue { <4 x float>, <4 x float>, <4 x float>, float } %call, 0303 %v5 = extractvalue { <4 x float>, <4 x float>, <4 x float>, float } %call, 1304 %v6 = extractvalue { <4 x float>, <4 x float>, <4 x float>, float } %call, 2305 %v8 = extractvalue { <4 x float>, <4 x float>, <4 x float>, float } %call, 3306 307 %add = fadd <4 x float> %v3, %v5308 %add1 = fadd <4 x float> %add, %v6309 %res.0 = insertvalue { <4 x float>, float } undef, <4 x float> %add1, 0310 %res = insertvalue { <4 x float>, float } %res.0, float %v8, 1311 ret { <4 x float>, float } %res312}313 314declare swiftcc { <4 x float>, <4 x float>, <4 x float>, float } @gen12()315