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1; RUN: llc < %s -mcpu=swift -mtriple=armv7s-apple-ios | FileCheck %s2; RUN: llc < %s -arm-assume-misaligned-load-store -mcpu=swift -mtriple=armv7s-apple-ios | FileCheck %s3 4; Check that we avoid producing vldm instructions using d registers that5; begin in the most-significant half of a q register. These require more6; micro-ops on swift and so aren't worth combining.7 8; CHECK-LABEL: test_vldm9; CHECK: vldmia r{{[0-9]+}}, {d2, d3, d4}10; CHECK-NOT: vldmia r{{[0-9]+}}, {d1, d2, d3, d4}11 12declare fastcc void @force_register(double %d0, double %d1, double %d2, double %d3, double %d4) 13 14define void @test_vldm(ptr %x, ptr %y) {15entry:16 %addr1 = getelementptr double, ptr %x, i32 117 %addr2 = getelementptr double, ptr %x, i32 218 %addr3 = getelementptr double, ptr %x, i32 319 %d0 = load double , ptr %y20 %d1 = load double , ptr %x21 %d2 = load double , ptr %addr122 %d3 = load double , ptr %addr223 %d4 = load double , ptr %addr324 ; We are trying to force x[0-3] in registers d1 to d4 so that we can test we25 ; don't form a "vldmia rX, {d1, d2, d3, d4}".26 ; We are relying on the calling convention and that register allocation27 ; properly coalesces registers.28 call fastcc void @force_register(double %d0, double %d1, double %d2, double %d3, double %d4)29 ret void30}31