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1; RUN: llc < %s -mtriple=armv7-apple-ios -mcpu=cortex-a9 -stress-ivchain | FileCheck %s2; REQUIRES: asserts3 4; @sharedidx is an unrolled variant of this loop:5; for (unsigned long i = 0; i < len; i += s) {6; c[i] = a[i] + b[i];7; }8; where 's' cannot be folded into the addressing mode.9;10; This is not quite profitable to chain. But with -stress-ivchain, we11; can form three address chains in place of the shared induction12; variable.13 14; rdar://1067443015define void @sharedidx(ptr nocapture %a, ptr nocapture %b, ptr nocapture %c, i32 %s, i32 %len) nounwind ssp {16entry:17; CHECK-LABEL: sharedidx:18 %cmp8 = icmp eq i32 %len, 019 br i1 %cmp8, label %for.end, label %for.body20 21for.body: ; preds = %entry, %for.body.322; CHECK: %for.body23; CHECK: ldrb {{r[0-9]+|lr}}, [{{r[0-9]+|lr}}, {{r[0-9]+|lr}}]!24; CHECK: ldrb {{r[0-9]+|lr}}, [{{r[0-9]+|lr}}, {{r[0-9]+|lr}}]!25 %i.09 = phi i32 [ %add5.3, %for.body.3 ], [ 0, %entry ]26 %arrayidx = getelementptr inbounds i8, ptr %a, i32 %i.0927 %0 = load i8, ptr %arrayidx, align 128 %conv6 = zext i8 %0 to i3229 %arrayidx1 = getelementptr inbounds i8, ptr %b, i32 %i.0930 %1 = load i8, ptr %arrayidx1, align 131 %conv27 = zext i8 %1 to i3232 %add = add nsw i32 %conv27, %conv633 %conv3 = trunc i32 %add to i834 %arrayidx4 = getelementptr inbounds i8, ptr %c, i32 %i.0935 store i8 %conv3, ptr %arrayidx4, align 136 %add5 = add i32 %i.09, %s37 %cmp = icmp ult i32 %add5, %len38 br i1 %cmp, label %for.body.1, label %for.end39 40for.end: ; preds = %for.body, %for.body.1, %for.body.2, %for.body.3, %entry41 ret void42 43for.body.1: ; preds = %for.body44; CHECK: %for.body.145; CHECK: ldrb {{r[0-9]+|lr}}, [{{r[0-9]+|lr}}, {{r[0-9]+|lr}}]!46; CHECK: ldrb {{r[0-9]+|lr}}, [{{r[0-9]+|lr}}, {{r[0-9]+|lr}}]!47 %arrayidx.1 = getelementptr inbounds i8, ptr %a, i32 %add548 %2 = load i8, ptr %arrayidx.1, align 149 %conv6.1 = zext i8 %2 to i3250 %arrayidx1.1 = getelementptr inbounds i8, ptr %b, i32 %add551 %3 = load i8, ptr %arrayidx1.1, align 152 %conv27.1 = zext i8 %3 to i3253 %add.1 = add nsw i32 %conv27.1, %conv6.154 %conv3.1 = trunc i32 %add.1 to i855 %arrayidx4.1 = getelementptr inbounds i8, ptr %c, i32 %add556 store i8 %conv3.1, ptr %arrayidx4.1, align 157 %add5.1 = add i32 %add5, %s58 %cmp.1 = icmp ult i32 %add5.1, %len59 br i1 %cmp.1, label %for.body.2, label %for.end60 61for.body.2: ; preds = %for.body.162 %arrayidx.2 = getelementptr inbounds i8, ptr %a, i32 %add5.163 %4 = load i8, ptr %arrayidx.2, align 164 %conv6.2 = zext i8 %4 to i3265 %arrayidx1.2 = getelementptr inbounds i8, ptr %b, i32 %add5.166 %5 = load i8, ptr %arrayidx1.2, align 167 %conv27.2 = zext i8 %5 to i3268 %add.2 = add nsw i32 %conv27.2, %conv6.269 %conv3.2 = trunc i32 %add.2 to i870 %arrayidx4.2 = getelementptr inbounds i8, ptr %c, i32 %add5.171 store i8 %conv3.2, ptr %arrayidx4.2, align 172 %add5.2 = add i32 %add5.1, %s73 %cmp.2 = icmp ult i32 %add5.2, %len74 br i1 %cmp.2, label %for.body.3, label %for.end75 76for.body.3: ; preds = %for.body.277; CHECK: %for.body.378; CHECK: ldrb {{r[0-9]+|lr}}, [{{r[0-9]+|lr}}, {{r[0-9]+|lr}}]79; CHECK: ldrb {{r[0-9]+|lr}}, [{{r[0-9]+|lr}}, {{r[0-9]+|lr}}]80 %arrayidx.3 = getelementptr inbounds i8, ptr %a, i32 %add5.281 %6 = load i8, ptr %arrayidx.3, align 182 %conv6.3 = zext i8 %6 to i3283 %arrayidx1.3 = getelementptr inbounds i8, ptr %b, i32 %add5.284 %7 = load i8, ptr %arrayidx1.3, align 185 %conv27.3 = zext i8 %7 to i3286 %add.3 = add nsw i32 %conv27.3, %conv6.387 %conv3.3 = trunc i32 %add.3 to i888 %arrayidx4.3 = getelementptr inbounds i8, ptr %c, i32 %add5.289 store i8 %conv3.3, ptr %arrayidx4.3, align 190 %add5.3 = add i32 %add5.2, %s91 %cmp.3 = icmp ult i32 %add5.3, %len92 br i1 %cmp.3, label %for.body, label %for.end93}94