57 lines · plain
1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -run-pass=peephole-opt %s -o - -verify-machineinstrs | FileCheck %s3 4# The and -> ands transform is sensitive to scheduling; make sure we don't5# transform cases which aren't legal.6 7--- |8 target triple = "armv7-unknown-unknown"9 define i32 @foo_transform(i32 %in) {10 ret i32 undef11 }12 define i32 @foo_notransform(i32 %in) {13 ret i32 undef14 }15 16...17---18name: foo_transform19tracksRegLiveness: true20body: |21 bb.0 (%ir-block.0):22 liveins: $r023 24 ; CHECK-LABEL: name: foo_transform25 ; CHECK: liveins: $r026 ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r027 ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 4, 14 /* CC::al */, $noreg, $noreg28 ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[COPY]], 1, 14 /* CC::al */, $noreg, def $cpsr29 ; CHECK: [[MOVCCi16_:%[0-9]+]]:gpr = MOVCCi16 [[MOVi]], 5, 0 /* CC::eq */, $cpsr30 ; CHECK: $r0 = COPY killed [[MOVCCi16_]]31 ; CHECK: $r1 = COPY killed [[ANDri]]32 ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0, implicit $r133 %1:gpr = COPY $r034 %2:gpr = MOVi 4, 14, $noreg, $noreg35 %4:gpr = ANDri %1:gpr, 1, 14, $noreg, $noreg36 TSTri %1:gpr, 1, 14, $noreg, implicit-def $cpsr37 %3:gpr = MOVCCi16 %2, 5, 0, $cpsr38 $r0 = COPY killed %339 $r1 = COPY killed %440 BX_RET 14, $noreg, implicit $r0, implicit $r141...42name: foo_notransform43tracksRegLiveness: true44body: |45 bb.0 (%ir-block.0):46 liveins: $r047 48 %1:gpr = COPY $r049 %2:gpr = MOVi 4, 14, $noreg, $noreg50 TSTri %1:gpr, 1, 14, $noreg, implicit-def $cpsr51 %3:gpr = MOVCCi16 %2, 5, 0, $cpsr52 %4:gpr = ANDri %1:gpr, 1, 14, $noreg, $noreg53 $r0 = COPY killed %354 $r1 = COPY killed %455 BX_RET 14, $noreg, implicit $r0, implicit $r156 57