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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=thumbv6m-none-eabi | FileCheck %s --check-prefix=CHECK-T13; RUN: llc < %s -mtriple=thumbv7m-none-eabi | FileCheck %s --check-prefix=CHECK-T2 --check-prefix=CHECK-T2NODSP4; RUN: llc < %s -mtriple=thumbv7em-none-eabi | FileCheck %s --check-prefix=CHECK-T2 --check-prefix=CHECK-T2DSP5; RUN: llc < %s -mtriple=armv8a-none-eabi | FileCheck %s --check-prefix=CHECK-ARM6 7declare i4 @llvm.uadd.sat.i4(i4, i4)8declare i8 @llvm.uadd.sat.i8(i8, i8)9declare i16 @llvm.uadd.sat.i16(i16, i16)10declare i32 @llvm.uadd.sat.i32(i32, i32)11declare i64 @llvm.uadd.sat.i64(i64, i64)12 13define i32 @func(i32 %x, i32 %y) nounwind {14; CHECK-T1-LABEL: func:15; CHECK-T1: @ %bb.0:16; CHECK-T1-NEXT: adds r0, r0, r117; CHECK-T1-NEXT: blo .LBB0_218; CHECK-T1-NEXT: @ %bb.1:19; CHECK-T1-NEXT: movs r0, #020; CHECK-T1-NEXT: mvns r0, r021; CHECK-T1-NEXT: .LBB0_2:22; CHECK-T1-NEXT: bx lr23;24; CHECK-T2-LABEL: func:25; CHECK-T2: @ %bb.0:26; CHECK-T2-NEXT: adds r0, r0, r127; CHECK-T2-NEXT: it hs28; CHECK-T2-NEXT: movhs.w r0, #-129; CHECK-T2-NEXT: bx lr30;31; CHECK-ARM-LABEL: func:32; CHECK-ARM: @ %bb.0:33; CHECK-ARM-NEXT: adds r0, r0, r134; CHECK-ARM-NEXT: mvnhs r0, #035; CHECK-ARM-NEXT: bx lr36 %tmp = call i32 @llvm.uadd.sat.i32(i32 %x, i32 %y)37 ret i32 %tmp38}39 40define i64 @func2(i64 %x, i64 %y) nounwind {41; CHECK-T1-LABEL: func2:42; CHECK-T1: @ %bb.0:43; CHECK-T1-NEXT: .save {r4, r5, r7, lr}44; CHECK-T1-NEXT: push {r4, r5, r7, lr}45; CHECK-T1-NEXT: movs r5, #046; CHECK-T1-NEXT: adds r4, r0, r247; CHECK-T1-NEXT: adcs r1, r348; CHECK-T1-NEXT: mov r0, r549; CHECK-T1-NEXT: adcs r0, r550; CHECK-T1-NEXT: mvns r2, r551; CHECK-T1-NEXT: cmp r0, #052; CHECK-T1-NEXT: mov r0, r253; CHECK-T1-NEXT: beq .LBB1_354; CHECK-T1-NEXT: @ %bb.1:55; CHECK-T1-NEXT: beq .LBB1_456; CHECK-T1-NEXT: .LBB1_2:57; CHECK-T1-NEXT: mov r1, r258; CHECK-T1-NEXT: pop {r4, r5, r7, pc}59; CHECK-T1-NEXT: .LBB1_3:60; CHECK-T1-NEXT: mov r0, r461; CHECK-T1-NEXT: bne .LBB1_262; CHECK-T1-NEXT: .LBB1_4:63; CHECK-T1-NEXT: mov r2, r164; CHECK-T1-NEXT: mov r1, r265; CHECK-T1-NEXT: pop {r4, r5, r7, pc}66;67; CHECK-T2-LABEL: func2:68; CHECK-T2: @ %bb.0:69; CHECK-T2-NEXT: adds r0, r0, r270; CHECK-T2-NEXT: mov.w r12, #071; CHECK-T2-NEXT: adcs r1, r372; CHECK-T2-NEXT: adcs r2, r12, #073; CHECK-T2-NEXT: itt ne74; CHECK-T2-NEXT: movne.w r0, #-175; CHECK-T2-NEXT: movne.w r1, #-176; CHECK-T2-NEXT: bx lr77;78; CHECK-ARM-LABEL: func2:79; CHECK-ARM: @ %bb.0:80; CHECK-ARM-NEXT: adds r0, r0, r281; CHECK-ARM-NEXT: mov r12, #082; CHECK-ARM-NEXT: adcs r1, r1, r383; CHECK-ARM-NEXT: adcs r2, r12, #084; CHECK-ARM-NEXT: mvnne r0, #085; CHECK-ARM-NEXT: mvnne r1, #086; CHECK-ARM-NEXT: bx lr87 %tmp = call i64 @llvm.uadd.sat.i64(i64 %x, i64 %y)88 ret i64 %tmp89}90 91define zeroext i16 @func16(i16 zeroext %x, i16 zeroext %y) nounwind {92; CHECK-T1-LABEL: func16:93; CHECK-T1: @ %bb.0:94; CHECK-T1-NEXT: adds r0, r0, r195; CHECK-T1-NEXT: ldr r1, .LCPI2_096; CHECK-T1-NEXT: cmp r0, r197; CHECK-T1-NEXT: blo .LBB2_298; CHECK-T1-NEXT: @ %bb.1:99; CHECK-T1-NEXT: mov r0, r1100; CHECK-T1-NEXT: .LBB2_2:101; CHECK-T1-NEXT: bx lr102; CHECK-T1-NEXT: .p2align 2103; CHECK-T1-NEXT: @ %bb.3:104; CHECK-T1-NEXT: .LCPI2_0:105; CHECK-T1-NEXT: .long 65535 @ 0xffff106;107; CHECK-T2NODSP-LABEL: func16:108; CHECK-T2NODSP: @ %bb.0:109; CHECK-T2NODSP-NEXT: add r1, r0110; CHECK-T2NODSP-NEXT: movw r0, #65535111; CHECK-T2NODSP-NEXT: cmp r1, r0112; CHECK-T2NODSP-NEXT: it lo113; CHECK-T2NODSP-NEXT: movlo r0, r1114; CHECK-T2NODSP-NEXT: bx lr115;116; CHECK-T2DSP-LABEL: func16:117; CHECK-T2DSP: @ %bb.0:118; CHECK-T2DSP-NEXT: uqadd16 r0, r0, r1119; CHECK-T2DSP-NEXT: uxth r0, r0120; CHECK-T2DSP-NEXT: bx lr121;122; CHECK-ARM-LABEL: func16:123; CHECK-ARM: @ %bb.0:124; CHECK-ARM-NEXT: uqadd16 r0, r0, r1125; CHECK-ARM-NEXT: uxth r0, r0126; CHECK-ARM-NEXT: bx lr127 %tmp = call i16 @llvm.uadd.sat.i16(i16 %x, i16 %y)128 ret i16 %tmp129}130 131define zeroext i8 @func8(i8 zeroext %x, i8 zeroext %y) nounwind {132; CHECK-T1-LABEL: func8:133; CHECK-T1: @ %bb.0:134; CHECK-T1-NEXT: adds r0, r0, r1135; CHECK-T1-NEXT: cmp r0, #255136; CHECK-T1-NEXT: blo .LBB3_2137; CHECK-T1-NEXT: @ %bb.1:138; CHECK-T1-NEXT: movs r0, #255139; CHECK-T1-NEXT: .LBB3_2:140; CHECK-T1-NEXT: bx lr141;142; CHECK-T2NODSP-LABEL: func8:143; CHECK-T2NODSP: @ %bb.0:144; CHECK-T2NODSP-NEXT: add r0, r1145; CHECK-T2NODSP-NEXT: cmp r0, #255146; CHECK-T2NODSP-NEXT: it hs147; CHECK-T2NODSP-NEXT: movhs r0, #255148; CHECK-T2NODSP-NEXT: bx lr149;150; CHECK-T2DSP-LABEL: func8:151; CHECK-T2DSP: @ %bb.0:152; CHECK-T2DSP-NEXT: uqadd8 r0, r0, r1153; CHECK-T2DSP-NEXT: uxtb r0, r0154; CHECK-T2DSP-NEXT: bx lr155;156; CHECK-ARM-LABEL: func8:157; CHECK-ARM: @ %bb.0:158; CHECK-ARM-NEXT: uqadd8 r0, r0, r1159; CHECK-ARM-NEXT: uxtb r0, r0160; CHECK-ARM-NEXT: bx lr161 %tmp = call i8 @llvm.uadd.sat.i8(i8 %x, i8 %y)162 ret i8 %tmp163}164 165define zeroext i4 @func3(i4 zeroext %x, i4 zeroext %y) nounwind {166; CHECK-T1-LABEL: func3:167; CHECK-T1: @ %bb.0:168; CHECK-T1-NEXT: adds r0, r0, r1169; CHECK-T1-NEXT: cmp r0, #15170; CHECK-T1-NEXT: blo .LBB4_2171; CHECK-T1-NEXT: @ %bb.1:172; CHECK-T1-NEXT: movs r0, #15173; CHECK-T1-NEXT: .LBB4_2:174; CHECK-T1-NEXT: bx lr175;176; CHECK-T2-LABEL: func3:177; CHECK-T2: @ %bb.0:178; CHECK-T2-NEXT: add r0, r1179; CHECK-T2-NEXT: cmp r0, #15180; CHECK-T2-NEXT: it hs181; CHECK-T2-NEXT: movhs r0, #15182; CHECK-T2-NEXT: bx lr183;184; CHECK-ARM-LABEL: func3:185; CHECK-ARM: @ %bb.0:186; CHECK-ARM-NEXT: add r0, r0, r1187; CHECK-ARM-NEXT: cmp r0, #15188; CHECK-ARM-NEXT: movhs r0, #15189; CHECK-ARM-NEXT: bx lr190 %tmp = call i4 @llvm.uadd.sat.i4(i4 %x, i4 %y)191 ret i4 %tmp192}193