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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=thumbv6m-none-eabi | FileCheck %s --check-prefix=CHECK-T13; RUN: llc < %s -mtriple=thumbv7m-none-eabi | FileCheck %s --check-prefix=CHECK-T2 --check-prefix=CHECK-T2NODSP4; RUN: llc < %s -mtriple=thumbv7em-none-eabi | FileCheck %s --check-prefix=CHECK-T2 --check-prefix=CHECK-T2DSP5; RUN: llc < %s -mtriple=armv8a-none-eabi | FileCheck %s --check-prefix=CHECK-ARM6 7declare i4 @llvm.uadd.sat.i4(i4, i4)8declare i8 @llvm.uadd.sat.i8(i8, i8)9declare i16 @llvm.uadd.sat.i16(i16, i16)10declare i32 @llvm.uadd.sat.i32(i32, i32)11declare i64 @llvm.uadd.sat.i64(i64, i64)12 13define i32 @func32(i32 %x, i32 %y, i32 %z) nounwind {14; CHECK-T1-LABEL: func32:15; CHECK-T1: @ %bb.0:16; CHECK-T1-NEXT: muls r1, r2, r117; CHECK-T1-NEXT: adds r0, r0, r118; CHECK-T1-NEXT: blo .LBB0_219; CHECK-T1-NEXT: @ %bb.1:20; CHECK-T1-NEXT: movs r0, #021; CHECK-T1-NEXT: mvns r0, r022; CHECK-T1-NEXT: .LBB0_2:23; CHECK-T1-NEXT: bx lr24;25; CHECK-T2-LABEL: func32:26; CHECK-T2: @ %bb.0:27; CHECK-T2-NEXT: muls r1, r2, r128; CHECK-T2-NEXT: adds r0, r0, r129; CHECK-T2-NEXT: it hs30; CHECK-T2-NEXT: movhs.w r0, #-131; CHECK-T2-NEXT: bx lr32;33; CHECK-ARM-LABEL: func32:34; CHECK-ARM: @ %bb.0:35; CHECK-ARM-NEXT: mul r1, r1, r236; CHECK-ARM-NEXT: adds r0, r0, r137; CHECK-ARM-NEXT: mvnhs r0, #038; CHECK-ARM-NEXT: bx lr39 %a = mul i32 %y, %z40 %tmp = call i32 @llvm.uadd.sat.i32(i32 %x, i32 %a)41 ret i32 %tmp42}43 44define i64 @func64(i64 %x, i64 %y, i64 %z) nounwind {45; CHECK-T1-LABEL: func64:46; CHECK-T1: @ %bb.0:47; CHECK-T1-NEXT: .save {r4, lr}48; CHECK-T1-NEXT: push {r4, lr}49; CHECK-T1-NEXT: movs r4, #050; CHECK-T1-NEXT: ldr r2, [sp, #12]51; CHECK-T1-NEXT: ldr r3, [sp, #8]52; CHECK-T1-NEXT: adds r3, r0, r353; CHECK-T1-NEXT: adcs r2, r154; CHECK-T1-NEXT: mov r0, r455; CHECK-T1-NEXT: adcs r0, r456; CHECK-T1-NEXT: mvns r1, r457; CHECK-T1-NEXT: cmp r0, #058; CHECK-T1-NEXT: mov r0, r159; CHECK-T1-NEXT: beq .LBB1_360; CHECK-T1-NEXT: @ %bb.1:61; CHECK-T1-NEXT: beq .LBB1_462; CHECK-T1-NEXT: .LBB1_2:63; CHECK-T1-NEXT: pop {r4, pc}64; CHECK-T1-NEXT: .LBB1_3:65; CHECK-T1-NEXT: mov r0, r366; CHECK-T1-NEXT: bne .LBB1_267; CHECK-T1-NEXT: .LBB1_4:68; CHECK-T1-NEXT: mov r1, r269; CHECK-T1-NEXT: pop {r4, pc}70;71; CHECK-T2-LABEL: func64:72; CHECK-T2: @ %bb.0:73; CHECK-T2-NEXT: ldrd r2, r3, [sp]74; CHECK-T2-NEXT: mov.w r12, #075; CHECK-T2-NEXT: adds r0, r0, r276; CHECK-T2-NEXT: adcs r1, r377; CHECK-T2-NEXT: adcs r2, r12, #078; CHECK-T2-NEXT: itt ne79; CHECK-T2-NEXT: movne.w r0, #-180; CHECK-T2-NEXT: movne.w r1, #-181; CHECK-T2-NEXT: bx lr82;83; CHECK-ARM-LABEL: func64:84; CHECK-ARM: @ %bb.0:85; CHECK-ARM-NEXT: ldr r2, [sp]86; CHECK-ARM-NEXT: mov r12, #087; CHECK-ARM-NEXT: ldr r3, [sp, #4]88; CHECK-ARM-NEXT: adds r0, r0, r289; CHECK-ARM-NEXT: adcs r1, r1, r390; CHECK-ARM-NEXT: adcs r2, r12, #091; CHECK-ARM-NEXT: mvnne r0, #092; CHECK-ARM-NEXT: mvnne r1, #093; CHECK-ARM-NEXT: bx lr94 %a = mul i64 %y, %z95 %tmp = call i64 @llvm.uadd.sat.i64(i64 %x, i64 %z)96 ret i64 %tmp97}98 99define zeroext i16 @func16(i16 zeroext %x, i16 zeroext %y, i16 zeroext %z) nounwind {100; CHECK-T1-LABEL: func16:101; CHECK-T1: @ %bb.0:102; CHECK-T1-NEXT: muls r1, r2, r1103; CHECK-T1-NEXT: uxth r1, r1104; CHECK-T1-NEXT: adds r0, r0, r1105; CHECK-T1-NEXT: ldr r1, .LCPI2_0106; CHECK-T1-NEXT: cmp r0, r1107; CHECK-T1-NEXT: blo .LBB2_2108; CHECK-T1-NEXT: @ %bb.1:109; CHECK-T1-NEXT: mov r0, r1110; CHECK-T1-NEXT: .LBB2_2:111; CHECK-T1-NEXT: bx lr112; CHECK-T1-NEXT: .p2align 2113; CHECK-T1-NEXT: @ %bb.3:114; CHECK-T1-NEXT: .LCPI2_0:115; CHECK-T1-NEXT: .long 65535 @ 0xffff116;117; CHECK-T2NODSP-LABEL: func16:118; CHECK-T2NODSP: @ %bb.0:119; CHECK-T2NODSP-NEXT: muls r1, r2, r1120; CHECK-T2NODSP-NEXT: uxth r1, r1121; CHECK-T2NODSP-NEXT: add r1, r0122; CHECK-T2NODSP-NEXT: movw r0, #65535123; CHECK-T2NODSP-NEXT: cmp r1, r0124; CHECK-T2NODSP-NEXT: it lo125; CHECK-T2NODSP-NEXT: movlo r0, r1126; CHECK-T2NODSP-NEXT: bx lr127;128; CHECK-T2DSP-LABEL: func16:129; CHECK-T2DSP: @ %bb.0:130; CHECK-T2DSP-NEXT: muls r1, r2, r1131; CHECK-T2DSP-NEXT: uqadd16 r0, r0, r1132; CHECK-T2DSP-NEXT: uxth r0, r0133; CHECK-T2DSP-NEXT: bx lr134;135; CHECK-ARM-LABEL: func16:136; CHECK-ARM: @ %bb.0:137; CHECK-ARM-NEXT: mul r1, r1, r2138; CHECK-ARM-NEXT: uqadd16 r0, r0, r1139; CHECK-ARM-NEXT: uxth r0, r0140; CHECK-ARM-NEXT: bx lr141 %a = mul i16 %y, %z142 %tmp = call i16 @llvm.uadd.sat.i16(i16 %x, i16 %a)143 ret i16 %tmp144}145 146define zeroext i8 @func8(i8 zeroext %x, i8 zeroext %y, i8 zeroext %z) nounwind {147; CHECK-T1-LABEL: func8:148; CHECK-T1: @ %bb.0:149; CHECK-T1-NEXT: muls r1, r2, r1150; CHECK-T1-NEXT: uxtb r1, r1151; CHECK-T1-NEXT: adds r0, r0, r1152; CHECK-T1-NEXT: cmp r0, #255153; CHECK-T1-NEXT: blo .LBB3_2154; CHECK-T1-NEXT: @ %bb.1:155; CHECK-T1-NEXT: movs r0, #255156; CHECK-T1-NEXT: .LBB3_2:157; CHECK-T1-NEXT: bx lr158;159; CHECK-T2NODSP-LABEL: func8:160; CHECK-T2NODSP: @ %bb.0:161; CHECK-T2NODSP-NEXT: muls r1, r2, r1162; CHECK-T2NODSP-NEXT: uxtb r1, r1163; CHECK-T2NODSP-NEXT: add r0, r1164; CHECK-T2NODSP-NEXT: cmp r0, #255165; CHECK-T2NODSP-NEXT: it hs166; CHECK-T2NODSP-NEXT: movhs r0, #255167; CHECK-T2NODSP-NEXT: bx lr168;169; CHECK-T2DSP-LABEL: func8:170; CHECK-T2DSP: @ %bb.0:171; CHECK-T2DSP-NEXT: muls r1, r2, r1172; CHECK-T2DSP-NEXT: uqadd8 r0, r0, r1173; CHECK-T2DSP-NEXT: uxtb r0, r0174; CHECK-T2DSP-NEXT: bx lr175;176; CHECK-ARM-LABEL: func8:177; CHECK-ARM: @ %bb.0:178; CHECK-ARM-NEXT: smulbb r1, r1, r2179; CHECK-ARM-NEXT: uqadd8 r0, r0, r1180; CHECK-ARM-NEXT: uxtb r0, r0181; CHECK-ARM-NEXT: bx lr182 %a = mul i8 %y, %z183 %tmp = call i8 @llvm.uadd.sat.i8(i8 %x, i8 %a)184 ret i8 %tmp185}186 187define zeroext i4 @func4(i4 zeroext %x, i4 zeroext %y, i4 zeroext %z) nounwind {188; CHECK-T1-LABEL: func4:189; CHECK-T1: @ %bb.0:190; CHECK-T1-NEXT: muls r1, r2, r1191; CHECK-T1-NEXT: movs r2, #15192; CHECK-T1-NEXT: ands r1, r2193; CHECK-T1-NEXT: adds r0, r0, r1194; CHECK-T1-NEXT: cmp r0, #15195; CHECK-T1-NEXT: blo .LBB4_2196; CHECK-T1-NEXT: @ %bb.1:197; CHECK-T1-NEXT: mov r0, r2198; CHECK-T1-NEXT: .LBB4_2:199; CHECK-T1-NEXT: bx lr200;201; CHECK-T2-LABEL: func4:202; CHECK-T2: @ %bb.0:203; CHECK-T2-NEXT: muls r1, r2, r1204; CHECK-T2-NEXT: and r1, r1, #15205; CHECK-T2-NEXT: add r0, r1206; CHECK-T2-NEXT: cmp r0, #15207; CHECK-T2-NEXT: it hs208; CHECK-T2-NEXT: movhs r0, #15209; CHECK-T2-NEXT: bx lr210;211; CHECK-ARM-LABEL: func4:212; CHECK-ARM: @ %bb.0:213; CHECK-ARM-NEXT: smulbb r1, r1, r2214; CHECK-ARM-NEXT: and r1, r1, #15215; CHECK-ARM-NEXT: add r0, r0, r1216; CHECK-ARM-NEXT: cmp r0, #15217; CHECK-ARM-NEXT: movhs r0, #15218; CHECK-ARM-NEXT: bx lr219 %a = mul i4 %y, %z220 %tmp = call i4 @llvm.uadd.sat.i4(i4 %x, i4 %a)221 ret i4 %tmp222}223