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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=armv6-unknown-linux-gnu | FileCheck %s --check-prefixes=ARMV63; RUN: llc < %s -mtriple=armv7-unknown-linux-gnu | FileCheck %s --check-prefixes=ARMV74 5define { i64, i8 } @mulodi_test(i64 %l, i64 %r) unnamed_addr #0 {6; ARMV6-LABEL: mulodi_test:7; ARMV6: @ %bb.0: @ %start8; ARMV6-NEXT: push {r4, r5, r11, lr}9; ARMV6-NEXT: umull r12, lr, r1, r210; ARMV6-NEXT: umull r4, r5, r3, r011; ARMV6-NEXT: cmp lr, #012; ARMV6-NEXT: movne lr, #113; ARMV6-NEXT: cmp r3, #014; ARMV6-NEXT: movne r3, #115; ARMV6-NEXT: cmp r1, #016; ARMV6-NEXT: umull r0, r2, r0, r217; ARMV6-NEXT: movne r1, #118; ARMV6-NEXT: and r1, r1, r319; ARMV6-NEXT: cmp r5, #020; ARMV6-NEXT: orr r1, r1, lr21; ARMV6-NEXT: movne r5, #122; ARMV6-NEXT: orr r3, r1, r523; ARMV6-NEXT: add r1, r12, r424; ARMV6-NEXT: adds r1, r2, r125; ARMV6-NEXT: mov r5, #026; ARMV6-NEXT: adc r2, r5, #027; ARMV6-NEXT: orr r2, r3, r228; ARMV6-NEXT: pop {r4, r5, r11, pc}29;30; ARMV7-LABEL: mulodi_test:31; ARMV7: @ %bb.0: @ %start32; ARMV7-NEXT: push {r4, r5, r11, lr}33; ARMV7-NEXT: umull r12, lr, r3, r034; ARMV7-NEXT: cmp r3, #035; ARMV7-NEXT: movwne r3, #136; ARMV7-NEXT: cmp r1, #037; ARMV7-NEXT: umull r0, r4, r0, r238; ARMV7-NEXT: umull r2, r5, r1, r239; ARMV7-NEXT: movwne r1, #140; ARMV7-NEXT: and r1, r1, r341; ARMV7-NEXT: cmp r5, #042; ARMV7-NEXT: movwne r5, #143; ARMV7-NEXT: cmp lr, #044; ARMV7-NEXT: orr r1, r1, r545; ARMV7-NEXT: movwne lr, #146; ARMV7-NEXT: orr r3, r1, lr47; ARMV7-NEXT: add r1, r2, r1248; ARMV7-NEXT: mov r2, #049; ARMV7-NEXT: adds r1, r4, r150; ARMV7-NEXT: adc r2, r2, #051; ARMV7-NEXT: orr r2, r3, r252; ARMV7-NEXT: pop {r4, r5, r11, pc}53start:54 %0 = tail call { i64, i1 } @llvm.umul.with.overflow.i64(i64 %l, i64 %r) #255 %1 = extractvalue { i64, i1 } %0, 056 %2 = extractvalue { i64, i1 } %0, 157 %3 = zext i1 %2 to i858 %4 = insertvalue { i64, i8 } undef, i64 %1, 059 %5 = insertvalue { i64, i8 } %4, i8 %3, 160 ret { i64, i8 } %561}62 63; Function Attrs: nounwind readnone speculatable64declare { i64, i1 } @llvm.umul.with.overflow.i64(i64, i64) #165 66attributes #0 = { nounwind readnone uwtable }67attributes #1 = { nounwind readnone speculatable }68attributes #2 = { nounwind }69