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1; RUN: llc -mtriple armv6t2 %s -o - | FileCheck %s2; RUN: llc -mtriple thumbv6t2 %s -o - | FileCheck %s --check-prefix=CHECK-T23; RUN: llc -mtriple armv7 %s -o - | FileCheck %s4; RUN: llc -mtriple thumbv7 %s -o - | FileCheck %s --check-prefix=CHECK-T25; RUN: llc -mtriple thumbv7m %s -o - | FileCheck %s --check-prefix=CHECK-T26; RUN: llc -mtriple thumbv8m.main %s -o - | FileCheck %s --check-prefix=CHECK-T27 8; CHECK-LABEL: unfold19; CHECK-NOT: mov10; CHECK: orr r0, r0, #25511; CHECK: add r0, r1, r0, lsl #112; CHECK-T2-NOT: mov13; CHECK-T2: orr r0, r0, #25514; CHECK-T2: add.w r0, r1, r0, lsl #115define arm_aapcscc i32 @unfold1(i32 %a, i32 %b) {16entry:17 %or = shl i32 %a, 118 %shl = or i32 %or, 51019 %add = add nsw i32 %shl, %b20 ret i32 %add21}22 23; CHECK-LABEL: unfold224; CHECK-NOT: mov25; CHECK: orr r0, r0, #408026; CHECK: sub r0, r1, r0, lsl #227; CHECK-T2-NOT: mov28; CHECK-T2: orr r0, r0, #408029; CHECK-T2: sub.w r0, r1, r0, lsl #230define arm_aapcscc i32 @unfold2(i32 %a, i32 %b) {31entry:32 %or = shl i32 %a, 233 %shl = or i32 %or, 1632034 %sub = sub nsw i32 %b, %shl35 ret i32 %sub36}37 38; CHECK-LABEL: unfold339; CHECK-NOT: mov40; CHECK: orr r0, r0, #6528041; CHECK: and r0, r1, r0, lsl #442; CHECK-T2-NOT: mov43; CHECK-T2: orr r0, r0, #6528044; CHECK-T2: and.w r0, r1, r0, lsl #445define arm_aapcscc i32 @unfold3(i32 %a, i32 %b) {46entry:47 %or = shl i32 %a, 448 %shl = or i32 %or, 104448049 %and = and i32 %shl, %b50 ret i32 %and51}52 53; CHECK-LABEL: unfold454; CHECK-NOT: mov55; CHECK: orr r0, r0, #104448056; CHECK: eor r0, r1, r0, lsl #557; CHECK-T2-NOT: mov58; CHECK-T2: orr r0, r0, #104448059; CHECK-T2: eor.w r0, r1, r0, lsl #560define arm_aapcscc i32 @unfold4(i32 %a, i32 %b) {61entry:62 %or = shl i32 %a, 563 %shl = or i32 %or, 3342336064 %xor = xor i32 %shl, %b65 ret i32 %xor66}67 68; CHECK-LABEL: unfold569; CHECK-NOT: mov70; CHECK: add r0, r0, #49671; CHECK: orr r0, r1, r0, lsl #672; CHECK-T2: add.w r0, r0, #49673; CHECK-T2: orr.w r0, r1, r0, lsl #674define arm_aapcscc i32 @unfold5(i32 %a, i32 %b) {75entry:76 %add = shl i32 %a, 677 %shl = add i32 %add, 3174478 %or = or i32 %shl, %b79 ret i32 %or80}81 82; CHECK-LABEL: unfold683; CHECK-NOT: mov84; CHECK: add r0, r0, #793685; CHECK: and r0, r1, r0, lsl #886; CHECK-T2-NOT: mov87; CHECK-T2: add.w r0, r0, #793688; CHECK-T2: and.w r0, r1, r0, lsl #889define arm_aapcscc i32 @unfold6(i32 %a, i32 %b) {90entry:91 %add = shl i32 %a, 892 %shl = add i32 %add, 203161693 %and = and i32 %shl, %b94 ret i32 %and95}96 97; CHECK-LABEL: unfold798; CHECK-NOT: mov99; CHECK: and r0, r0, #256100; CHECK: add r0, r1, r0, lsl #1101; CHECK-T2-NOT: mov102; CHECK-T2: and r0, r0, #256103; CHECK-T2: add.w r0, r1, r0, lsl #1104define arm_aapcscc i32 @unfold7(i32 %a, i32 %b) {105entry:106 %shl = shl i32 %a, 1107 %and = and i32 %shl, 512108 %add = add nsw i32 %and, %b109 ret i32 %add110}111 112; CHECK-LABEL: unfold8113; CHECK-NOT: mov114; CHECK: add r0, r0, #126976115; CHECK: eor r0, r1, r0, lsl #9116; CHECK-T2-NOT: mov117; CHECK-T2: add.w r0, r0, #126976118; CHECK-T2: eor.w r0, r1, r0, lsl #9119define arm_aapcscc i32 @unfold8(i32 %a, i32 %b) {120entry:121 %add = shl i32 %a, 9122 %shl = add i32 %add, 65011712123 %xor = xor i32 %shl, %b124 ret i32 %xor125}126 127; CHECK-LABEL: unfold9128; CHECK-NOT: mov129; CHECK: eor r0, r0, #255130; CHECK: add r0, r1, r0, lsl #1131; CHECK-T2-NOT: mov132; CHECK-T2: eor r0, r0, #255133; CHECK-T2: add.w r0, r1, r0, lsl #1134define arm_aapcscc i32 @unfold9(i32 %a, i32 %b) {135entry:136 %shl = shl i32 %a, 1137 %xor = xor i32 %shl, 510138 %add = add nsw i32 %xor, %b139 ret i32 %add140}141 142; CHECK-LABEL: unfold10143; CHECK-NOT: mov r2144; CHECK: orr r2, r0, #4080145; CHECK: cmp r1, r2, lsl #10146; CHECK-T2-NOT: mov.w r2147; CHECK-T2: orr r2, r0, #4080148; CHECK-T2: cmp.w r1, r2, lsl #10149define arm_aapcscc i32 @unfold10(i32 %a, i32 %b) {150entry:151 %or = shl i32 %a, 10152 %shl = or i32 %or, 4177920153 %cmp = icmp sgt i32 %shl, %b154 %conv = zext i1 %cmp to i32155 ret i32 %conv156}157 158; CHECK-LABEL: unfold11159; CHECK-NOT: mov r2160; CHECK: add r2, r0, #7936161; CHECK: cmp r1, r2, lsl #11162; CHECK-T2-NOT: mov.w r2163; CHECK-T2: add.w r2, r0, #7936164; CHECK-T2: cmp.w r1, r2, lsl #11165define arm_aapcscc i32 @unfold11(i32 %a, i32 %b) {166entry:167 %add = shl i32 %a, 11168 %shl = add i32 %add, 16252928169 %cmp = icmp sgt i32 %shl, %b170 %conv = zext i1 %cmp to i32171 ret i32 %conv172}173 174