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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=arm-- -mattr=+fullfp16 < %s | FileCheck %s3 4define float @select_fneg_a_or_8_cmp_olt_a_neg8_f32(float %a, float %b) #0 {5; CHECK-LABEL: select_fneg_a_or_8_cmp_olt_a_neg8_f32:6; CHECK: @ %bb.0:7; CHECK-NEXT: vmov.f32 s0, #-8.000000e+008; CHECK-NEXT: vmov s2, r09; CHECK-NEXT: vminnm.f32 s0, s2, s010; CHECK-NEXT: vmov r0, s011; CHECK-NEXT: eor r0, r0, #-214748364812; CHECK-NEXT: mov pc, lr13 %fneg.a = fneg nnan nsz float %a14 %cmp.a = fcmp nnan nsz olt float %a, -8.015 %min.a = select nnan nsz i1 %cmp.a, float %fneg.a, float 8.016 ret float %min.a17}18 19define half @select_fneg_a_or_8_cmp_olt_a_neg8_f16(half %a, half %b) #0 {20; CHECK-LABEL: select_fneg_a_or_8_cmp_olt_a_neg8_f16:21; CHECK: @ %bb.0:22; CHECK-NEXT: vmov.f16 s0, #-8.000000e+0023; CHECK-NEXT: vmov.f16 s2, r024; CHECK-NEXT: vminnm.f16 s0, s2, s025; CHECK-NEXT: vneg.f16 s0, s026; CHECK-NEXT: vmov r0, s027; CHECK-NEXT: mov pc, lr28 %fneg.a = fneg nnan nsz half %a29 %cmp.a = fcmp nnan nsz olt half %a, -8.030 %min.a = select nnan nsz i1 %cmp.a, half %fneg.a, half 8.031 ret half %min.a32}33 34define float @select_fneg_a_or_8_cmp_ogt_a_neg8_f32(float %a, float %b) #0 {35; CHECK-LABEL: select_fneg_a_or_8_cmp_ogt_a_neg8_f32:36; CHECK: @ %bb.0:37; CHECK-NEXT: vmov.f32 s0, #-8.000000e+0038; CHECK-NEXT: vmov s2, r039; CHECK-NEXT: vmaxnm.f32 s0, s2, s040; CHECK-NEXT: vmov r0, s041; CHECK-NEXT: eor r0, r0, #-214748364842; CHECK-NEXT: mov pc, lr43 %fneg.a = fneg nnan nsz float %a44 %cmp.a = fcmp nnan nsz ogt float %a, -8.045 %min.a = select nnan nsz i1 %cmp.a, float %fneg.a, float 8.046 ret float %min.a47}48 49define half @select_fneg_a_or_8_cmp_ogt_a_neg8_f16(half %a, half %b) #0 {50; CHECK-LABEL: select_fneg_a_or_8_cmp_ogt_a_neg8_f16:51; CHECK: @ %bb.0:52; CHECK-NEXT: vmov.f16 s0, #-8.000000e+0053; CHECK-NEXT: vmov.f16 s2, r054; CHECK-NEXT: vmaxnm.f16 s0, s2, s055; CHECK-NEXT: vneg.f16 s0, s056; CHECK-NEXT: vmov r0, s057; CHECK-NEXT: mov pc, lr58 %fneg.a = fneg nnan nsz half %a59 %cmp.a = fcmp nnan nsz ogt half %a, -8.060 %min.a = select nnan nsz i1 %cmp.a, half %fneg.a, half 8.061 ret half %min.a62}63 64define float @select_fsub0_or_8_cmp_olt_fsub1_neg8_f32(float %a, float %b) #0 {65; CHECK-LABEL: select_fsub0_or_8_cmp_olt_fsub1_neg8_f32:66; CHECK: @ %bb.0:67; CHECK-NEXT: vmov.f32 s0, #4.000000e+0068; CHECK-NEXT: vmov s2, r069; CHECK-NEXT: vmov.f32 s4, #-8.000000e+0070; CHECK-NEXT: vsub.f32 s0, s0, s271; CHECK-NEXT: vminnm.f32 s0, s0, s472; CHECK-NEXT: vmov r0, s073; CHECK-NEXT: eor r0, r0, #-214748364874; CHECK-NEXT: mov pc, lr75 %sub.0 = fsub nnan nsz float 4.0, %a76 %sub.1 = fsub nnan nsz float %a, 4.077 %cmp.a = fcmp nnan nsz olt float %sub.0, -8.078 %min.a = select nnan nsz i1 %cmp.a, float %sub.1, float 8.079 ret float %min.a80}81 82define float @select_fsub0_or_neg8_cmp_olt_fsub1_8_f32(float %a, float %b) #0 {83; CHECK-LABEL: select_fsub0_or_neg8_cmp_olt_fsub1_8_f32:84; CHECK: @ %bb.0:85; CHECK-NEXT: vmov.f32 s0, #4.000000e+0086; CHECK-NEXT: vmov s2, r087; CHECK-NEXT: vmov.f32 s4, #8.000000e+0088; CHECK-NEXT: vsub.f32 s0, s0, s289; CHECK-NEXT: vminnm.f32 s0, s0, s490; CHECK-NEXT: vmov r0, s091; CHECK-NEXT: eor r0, r0, #-214748364892; CHECK-NEXT: mov pc, lr93 %sub.0 = fsub nnan nsz float 4.0, %a94 %sub.1 = fsub nnan nsz float %a, 4.095 %cmp.a = fcmp nnan nsz olt float %sub.0, 8.096 %min.a = select nnan nsz i1 %cmp.a, float %sub.1, float -8.097 ret float %min.a98}99 100define float @select_mul4_or_neg8_cmp_olt_mulneg4_8_f32(float %a, float %b) #0 {101; CHECK-LABEL: select_mul4_or_neg8_cmp_olt_mulneg4_8_f32:102; CHECK: @ %bb.0:103; CHECK-NEXT: vmov.f32 s0, #-4.000000e+00104; CHECK-NEXT: vmov s2, r0105; CHECK-NEXT: vmov.f32 s4, #8.000000e+00106; CHECK-NEXT: vmul.f32 s0, s2, s0107; CHECK-NEXT: vminnm.f32 s0, s0, s4108; CHECK-NEXT: vmov r0, s0109; CHECK-NEXT: eor r0, r0, #-2147483648110; CHECK-NEXT: mov pc, lr111 %mul.0 = fmul nnan nsz float %a, 4.0112 %mul.1 = fmul nnan nsz float %a, -4.0113 %cmp.a = fcmp nnan nsz olt float %mul.1, 8.0114 %min.a = select nnan nsz i1 %cmp.a, float %mul.0, float -8.0115 ret float %min.a116}117 118define float @select_mul4_or_8_cmp_olt_mulneg4_neg8_f32(float %a, float %b) #0 {119; CHECK-LABEL: select_mul4_or_8_cmp_olt_mulneg4_neg8_f32:120; CHECK: @ %bb.0:121; CHECK-NEXT: vmov.f32 s0, #-4.000000e+00122; CHECK-NEXT: vmov s2, r0123; CHECK-NEXT: vmov.f32 s4, #-8.000000e+00124; CHECK-NEXT: vmul.f32 s0, s2, s0125; CHECK-NEXT: vminnm.f32 s0, s0, s4126; CHECK-NEXT: vmov r0, s0127; CHECK-NEXT: eor r0, r0, #-2147483648128; CHECK-NEXT: mov pc, lr129 %mul.0 = fmul nnan nsz float %a, 4.0130 %mul.1 = fmul nnan nsz float %a, -4.0131 %cmp.a = fcmp nnan nsz olt float %mul.1, -8.0132 %min.a = select nnan nsz i1 %cmp.a, float %mul.0, float 8.0133 ret float %min.a134}135 136define float @select_mul4_or_8_cmp_olt_mulneg4_8_f32(float %a, float %b) #0 {137; CHECK-LABEL: select_mul4_or_8_cmp_olt_mulneg4_8_f32:138; CHECK: @ %bb.0:139; CHECK-NEXT: vmov.f32 s0, #-4.000000e+00140; CHECK-NEXT: vmov s2, r0141; CHECK-NEXT: vmov.f32 s6, #8.000000e+00142; CHECK-NEXT: vmov.f32 s4, #4.000000e+00143; CHECK-NEXT: vmul.f32 s0, s2, s0144; CHECK-NEXT: vmul.f32 s2, s2, s4145; CHECK-NEXT: vcmp.f32 s6, s0146; CHECK-NEXT: vmrs APSR_nzcv, fpscr147; CHECK-NEXT: vselgt.f32 s0, s2, s6148; CHECK-NEXT: vmov r0, s0149; CHECK-NEXT: mov pc, lr150 %mul.0 = fmul nnan nsz float %a, 4.0151 %mul.1 = fmul nnan nsz float %a, -4.0152 %cmp.a = fcmp nnan nsz olt float %mul.1, 8.0153 %min.a = select nnan nsz i1 %cmp.a, float %mul.0, float 8.0154 ret float %min.a155}156 157define float @select_mul4_or_neg8_cmp_olt_mulneg4_neg8_f32(float %a, float %b) #0 {158; CHECK-LABEL: select_mul4_or_neg8_cmp_olt_mulneg4_neg8_f32:159; CHECK: @ %bb.0:160; CHECK-NEXT: vmov.f32 s0, #-4.000000e+00161; CHECK-NEXT: vmov s2, r0162; CHECK-NEXT: vmov.f32 s6, #-8.000000e+00163; CHECK-NEXT: vmov.f32 s4, #4.000000e+00164; CHECK-NEXT: vmul.f32 s0, s2, s0165; CHECK-NEXT: vmul.f32 s2, s2, s4166; CHECK-NEXT: vcmp.f32 s6, s0167; CHECK-NEXT: vmrs APSR_nzcv, fpscr168; CHECK-NEXT: vselgt.f32 s0, s2, s6169; CHECK-NEXT: vmov r0, s0170; CHECK-NEXT: mov pc, lr171 %mul.0 = fmul nnan nsz float %a, 4.0172 %mul.1 = fmul nnan nsz float %a, -4.0173 %cmp.a = fcmp nnan nsz olt float %mul.1, -8.0174 %min.a = select nnan nsz i1 %cmp.a, float %mul.0, float -8.0175 ret float %min.a176}177 178define float @select_mulneg4_or_neg8_cmp_olt_mul4_8_f32(float %a, float %b) #0 {179; CHECK-LABEL: select_mulneg4_or_neg8_cmp_olt_mul4_8_f32:180; CHECK: @ %bb.0:181; CHECK-NEXT: vmov.f32 s0, #4.000000e+00182; CHECK-NEXT: vmov s2, r0183; CHECK-NEXT: vmov.f32 s4, #8.000000e+00184; CHECK-NEXT: vmul.f32 s0, s2, s0185; CHECK-NEXT: vminnm.f32 s0, s0, s4186; CHECK-NEXT: vmov r0, s0187; CHECK-NEXT: eor r0, r0, #-2147483648188; CHECK-NEXT: mov pc, lr189 %mul.0 = fmul nnan nsz float %a, -4.0190 %mul.1 = fmul nnan nsz float %a, 4.0191 %cmp.a = fcmp nnan nsz olt float %mul.1, 8.0192 %min.a = select nnan nsz i1 %cmp.a, float %mul.0, float -8.0193 ret float %min.a194}195 196; FIXME: Should be unnecessary197attributes #0 = { "no-signed-zeros-fp-math"="true" }198