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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=armv6-eabi %s -o - | FileCheck %s --check-prefixes=CHECK,ARMV63; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+dsp %s -o - | FileCheck %s --check-prefixes=CHECK,THUMB4 5define arm_aapcs_vfpcc i32 @usat_lsl(i32 %num){6; CHECK-LABEL: usat_lsl:7; CHECK: @ %bb.0: @ %entry8; CHECK-NEXT: usat r0, #7, r0, lsl #29; CHECK-NEXT: bx lr10entry:11 %shl = shl i32 %num, 212 %0 = tail call i32 @llvm.arm.usat(i32 %shl, i32 7)13 ret i32 %014}15 16define arm_aapcs_vfpcc i32 @usat_asr(i32 %num){17; CHECK-LABEL: usat_asr:18; CHECK: @ %bb.0: @ %entry19; CHECK-NEXT: usat r0, #7, r0, asr #220; CHECK-NEXT: bx lr21entry:22 %shr = ashr i32 %num, 223 %0 = tail call i32 @llvm.arm.usat(i32 %shr, i32 7)24 ret i32 %025}26 27define arm_aapcs_vfpcc i32 @usat_lsl2(i32 %num){28; ARMV6-LABEL: usat_lsl2:29; ARMV6: @ %bb.0: @ %entry30; ARMV6-NEXT: lsl r0, r0, #1531; ARMV6-NEXT: bic r1, r0, r0, asr #3132; ARMV6-NEXT: mov r0, #25533; ARMV6-NEXT: orr r0, r0, #3251234; ARMV6-NEXT: cmp r1, r035; ARMV6-NEXT: movlt r0, r136; ARMV6-NEXT: bx lr37;38; THUMB-LABEL: usat_lsl2:39; THUMB: @ %bb.0: @ %entry40; THUMB-NEXT: lsls r0, r0, #1541; THUMB-NEXT: movw r1, #3276742; THUMB-NEXT: bic.w r0, r0, r0, asr #3143; THUMB-NEXT: cmp r0, r144; THUMB-NEXT: csel r0, r0, r1, lt45; THUMB-NEXT: bx lr46entry:47 %shl = shl nsw i32 %num, 1548 %0 = icmp sgt i32 %shl, 049 %1 = select i1 %0, i32 %shl, i32 050 %2 = icmp slt i32 %1, 3276751 %3 = select i1 %2, i32 %1, i32 3276752 ret i32 %353}54 55define arm_aapcs_vfpcc i32 @usat_asr2(i32 %num){56; ARMV6-LABEL: usat_asr2:57; ARMV6: @ %bb.0: @ %entry58; ARMV6-NEXT: asr r1, r0, #1559; ARMV6-NEXT: bic r1, r1, r0, asr #3160; ARMV6-NEXT: mov r0, #25561; ARMV6-NEXT: orr r0, r0, #3251262; ARMV6-NEXT: cmp r1, r063; ARMV6-NEXT: movlt r0, r164; ARMV6-NEXT: bx lr65;66; THUMB-LABEL: usat_asr2:67; THUMB: @ %bb.0: @ %entry68; THUMB-NEXT: asrs r1, r0, #1569; THUMB-NEXT: bic.w r0, r1, r0, asr #3170; THUMB-NEXT: movw r1, #3276771; THUMB-NEXT: cmp r0, r172; THUMB-NEXT: csel r0, r0, r1, lt73; THUMB-NEXT: bx lr74entry:75 %shr = ashr i32 %num, 1576 %0 = icmp sgt i32 %shr, 077 %1 = select i1 %0, i32 %shr, i32 078 %2 = icmp slt i32 %1, 3276779 %3 = select i1 %2, i32 %1, i32 3276780 ret i32 %381}82 83declare i32 @llvm.arm.usat(i32, i32)84