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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=thumbv6m-none-eabi | FileCheck %s --check-prefix=CHECK-T13; RUN: llc < %s -mtriple=thumbv7m-none-eabi | FileCheck %s --check-prefix=CHECK-T2 --check-prefix=CHECK-T2NODSP4; RUN: llc < %s -mtriple=thumbv7em-none-eabi | FileCheck %s --check-prefix=CHECK-T2 --check-prefix=CHECK-T2DSP5; RUN: llc < %s -mtriple=armv8a-none-eabi | FileCheck %s --check-prefix=CHECK-ARM6 7declare i4 @llvm.usub.sat.i4(i4, i4)8declare i8 @llvm.usub.sat.i8(i8, i8)9declare i16 @llvm.usub.sat.i16(i16, i16)10declare i32 @llvm.usub.sat.i32(i32, i32)11declare i64 @llvm.usub.sat.i64(i64, i64)12 13define i32 @func32(i32 %x, i32 %y, i32 %z) nounwind {14; CHECK-T1-LABEL: func32:15; CHECK-T1: @ %bb.0:16; CHECK-T1-NEXT: muls r1, r2, r117; CHECK-T1-NEXT: subs r0, r0, r118; CHECK-T1-NEXT: bhs .LBB0_219; CHECK-T1-NEXT: @ %bb.1:20; CHECK-T1-NEXT: movs r0, #021; CHECK-T1-NEXT: .LBB0_2:22; CHECK-T1-NEXT: bx lr23;24; CHECK-T2-LABEL: func32:25; CHECK-T2: @ %bb.0:26; CHECK-T2-NEXT: muls r1, r2, r127; CHECK-T2-NEXT: subs r0, r0, r128; CHECK-T2-NEXT: it lo29; CHECK-T2-NEXT: movlo r0, #030; CHECK-T2-NEXT: bx lr31;32; CHECK-ARM-LABEL: func32:33; CHECK-ARM: @ %bb.0:34; CHECK-ARM-NEXT: mul r1, r1, r235; CHECK-ARM-NEXT: subs r0, r0, r136; CHECK-ARM-NEXT: movlo r0, #037; CHECK-ARM-NEXT: bx lr38 %a = mul i32 %y, %z39 %tmp = call i32 @llvm.usub.sat.i32(i32 %x, i32 %a)40 ret i32 %tmp41}42 43define i64 @func64(i64 %x, i64 %y, i64 %z) nounwind {44; CHECK-T1-LABEL: func64:45; CHECK-T1: @ %bb.0:46; CHECK-T1-NEXT: .save {r4, lr}47; CHECK-T1-NEXT: push {r4, lr}48; CHECK-T1-NEXT: mov r2, r149; CHECK-T1-NEXT: movs r1, #050; CHECK-T1-NEXT: ldr r4, [sp, #12]51; CHECK-T1-NEXT: ldr r3, [sp, #8]52; CHECK-T1-NEXT: subs r3, r0, r353; CHECK-T1-NEXT: sbcs r2, r454; CHECK-T1-NEXT: mov r0, r155; CHECK-T1-NEXT: adcs r0, r156; CHECK-T1-NEXT: movs r4, #157; CHECK-T1-NEXT: eors r4, r058; CHECK-T1-NEXT: cmp r4, #059; CHECK-T1-NEXT: mov r0, r160; CHECK-T1-NEXT: beq .LBB1_361; CHECK-T1-NEXT: @ %bb.1:62; CHECK-T1-NEXT: beq .LBB1_463; CHECK-T1-NEXT: .LBB1_2:64; CHECK-T1-NEXT: pop {r4, pc}65; CHECK-T1-NEXT: .LBB1_3:66; CHECK-T1-NEXT: mov r0, r367; CHECK-T1-NEXT: bne .LBB1_268; CHECK-T1-NEXT: .LBB1_4:69; CHECK-T1-NEXT: mov r1, r270; CHECK-T1-NEXT: pop {r4, pc}71;72; CHECK-T2-LABEL: func64:73; CHECK-T2: @ %bb.0:74; CHECK-T2-NEXT: ldrd r2, r3, [sp]75; CHECK-T2-NEXT: mov.w r12, #076; CHECK-T2-NEXT: subs r0, r0, r277; CHECK-T2-NEXT: sbcs r1, r378; CHECK-T2-NEXT: adc r2, r12, #079; CHECK-T2-NEXT: teq.w r2, #180; CHECK-T2-NEXT: itt ne81; CHECK-T2-NEXT: movne r0, #082; CHECK-T2-NEXT: movne r1, #083; CHECK-T2-NEXT: bx lr84;85; CHECK-ARM-LABEL: func64:86; CHECK-ARM: @ %bb.0:87; CHECK-ARM-NEXT: ldr r2, [sp]88; CHECK-ARM-NEXT: mov r12, #089; CHECK-ARM-NEXT: ldr r3, [sp, #4]90; CHECK-ARM-NEXT: subs r0, r0, r291; CHECK-ARM-NEXT: sbcs r1, r1, r392; CHECK-ARM-NEXT: adc r2, r12, #093; CHECK-ARM-NEXT: teq r2, #194; CHECK-ARM-NEXT: movwne r0, #095; CHECK-ARM-NEXT: movwne r1, #096; CHECK-ARM-NEXT: bx lr97 %a = mul i64 %y, %z98 %tmp = call i64 @llvm.usub.sat.i64(i64 %x, i64 %z)99 ret i64 %tmp100}101 102define zeroext i16 @func16(i16 zeroext %x, i16 zeroext %y, i16 zeroext %z) nounwind {103; CHECK-T1-LABEL: func16:104; CHECK-T1: @ %bb.0:105; CHECK-T1-NEXT: muls r1, r2, r1106; CHECK-T1-NEXT: uxth r1, r1107; CHECK-T1-NEXT: subs r0, r0, r1108; CHECK-T1-NEXT: bhs .LBB2_2109; CHECK-T1-NEXT: @ %bb.1:110; CHECK-T1-NEXT: movs r0, #0111; CHECK-T1-NEXT: .LBB2_2:112; CHECK-T1-NEXT: bx lr113;114; CHECK-T2NODSP-LABEL: func16:115; CHECK-T2NODSP: @ %bb.0:116; CHECK-T2NODSP-NEXT: muls r1, r2, r1117; CHECK-T2NODSP-NEXT: uxth r1, r1118; CHECK-T2NODSP-NEXT: subs r0, r0, r1119; CHECK-T2NODSP-NEXT: it lo120; CHECK-T2NODSP-NEXT: movlo r0, #0121; CHECK-T2NODSP-NEXT: bx lr122;123; CHECK-T2DSP-LABEL: func16:124; CHECK-T2DSP: @ %bb.0:125; CHECK-T2DSP-NEXT: muls r1, r2, r1126; CHECK-T2DSP-NEXT: uqsub16 r0, r0, r1127; CHECK-T2DSP-NEXT: uxth r0, r0128; CHECK-T2DSP-NEXT: bx lr129;130; CHECK-ARM-LABEL: func16:131; CHECK-ARM: @ %bb.0:132; CHECK-ARM-NEXT: mul r1, r1, r2133; CHECK-ARM-NEXT: uqsub16 r0, r0, r1134; CHECK-ARM-NEXT: uxth r0, r0135; CHECK-ARM-NEXT: bx lr136 %a = mul i16 %y, %z137 %tmp = call i16 @llvm.usub.sat.i16(i16 %x, i16 %a)138 ret i16 %tmp139}140 141define zeroext i8 @func8(i8 zeroext %x, i8 zeroext %y, i8 zeroext %z) nounwind {142; CHECK-T1-LABEL: func8:143; CHECK-T1: @ %bb.0:144; CHECK-T1-NEXT: muls r1, r2, r1145; CHECK-T1-NEXT: uxtb r1, r1146; CHECK-T1-NEXT: subs r0, r0, r1147; CHECK-T1-NEXT: bhs .LBB3_2148; CHECK-T1-NEXT: @ %bb.1:149; CHECK-T1-NEXT: movs r0, #0150; CHECK-T1-NEXT: .LBB3_2:151; CHECK-T1-NEXT: bx lr152;153; CHECK-T2NODSP-LABEL: func8:154; CHECK-T2NODSP: @ %bb.0:155; CHECK-T2NODSP-NEXT: muls r1, r2, r1156; CHECK-T2NODSP-NEXT: uxtb r1, r1157; CHECK-T2NODSP-NEXT: subs r0, r0, r1158; CHECK-T2NODSP-NEXT: it lo159; CHECK-T2NODSP-NEXT: movlo r0, #0160; CHECK-T2NODSP-NEXT: bx lr161;162; CHECK-T2DSP-LABEL: func8:163; CHECK-T2DSP: @ %bb.0:164; CHECK-T2DSP-NEXT: muls r1, r2, r1165; CHECK-T2DSP-NEXT: uqsub8 r0, r0, r1166; CHECK-T2DSP-NEXT: uxtb r0, r0167; CHECK-T2DSP-NEXT: bx lr168;169; CHECK-ARM-LABEL: func8:170; CHECK-ARM: @ %bb.0:171; CHECK-ARM-NEXT: smulbb r1, r1, r2172; CHECK-ARM-NEXT: uqsub8 r0, r0, r1173; CHECK-ARM-NEXT: uxtb r0, r0174; CHECK-ARM-NEXT: bx lr175 %a = mul i8 %y, %z176 %tmp = call i8 @llvm.usub.sat.i8(i8 %x, i8 %a)177 ret i8 %tmp178}179 180define zeroext i4 @func4(i4 zeroext %x, i4 zeroext %y, i4 zeroext %z) nounwind {181; CHECK-T1-LABEL: func4:182; CHECK-T1: @ %bb.0:183; CHECK-T1-NEXT: muls r1, r2, r1184; CHECK-T1-NEXT: movs r2, #15185; CHECK-T1-NEXT: ands r2, r1186; CHECK-T1-NEXT: subs r0, r0, r2187; CHECK-T1-NEXT: bhs .LBB4_2188; CHECK-T1-NEXT: @ %bb.1:189; CHECK-T1-NEXT: movs r0, #0190; CHECK-T1-NEXT: .LBB4_2:191; CHECK-T1-NEXT: bx lr192;193; CHECK-T2-LABEL: func4:194; CHECK-T2: @ %bb.0:195; CHECK-T2-NEXT: muls r1, r2, r1196; CHECK-T2-NEXT: and r1, r1, #15197; CHECK-T2-NEXT: subs r0, r0, r1198; CHECK-T2-NEXT: it lo199; CHECK-T2-NEXT: movlo r0, #0200; CHECK-T2-NEXT: bx lr201;202; CHECK-ARM-LABEL: func4:203; CHECK-ARM: @ %bb.0:204; CHECK-ARM-NEXT: smulbb r1, r1, r2205; CHECK-ARM-NEXT: and r1, r1, #15206; CHECK-ARM-NEXT: subs r0, r0, r1207; CHECK-ARM-NEXT: movlo r0, #0208; CHECK-ARM-NEXT: bx lr209 %a = mul i4 %y, %z210 %tmp = call i4 @llvm.usub.sat.i4(i4 %x, i4 %a)211 ret i4 %tmp212}213