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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=arm-eabi -mattr=+v6 | FileCheck %s --check-prefixes=CHECK,CHECK-V63; RUN: llc < %s -mtriple=arm-eabi -mattr=+v7 | FileCheck %s --check-prefixes=CHECK,CHECK-V74 5define zeroext i8 @test1(i32 %A.u) {6; CHECK-LABEL: test1:7; CHECK: @ %bb.0:8; CHECK-NEXT: uxtb r0, r09; CHECK-NEXT: bx lr10 %B.u = trunc i32 %A.u to i811 ret i8 %B.u12}13 14define zeroext i32 @test2(i32 %A.u, i32 %B.u) {15; CHECK-LABEL: test2:16; CHECK: @ %bb.0:17; CHECK-NEXT: uxtab r0, r0, r118; CHECK-NEXT: bx lr19 %C.u = trunc i32 %B.u to i820 %D.u = zext i8 %C.u to i3221 %E.u = add i32 %A.u, %D.u22 ret i32 %E.u23}24 25define zeroext i32 @test3(i32 %A.u) {26; CHECK-V6-LABEL: test3:27; CHECK-V6: @ %bb.0:28; CHECK-V6-NEXT: lsr r0, r0, #829; CHECK-V6-NEXT: uxth r0, r030; CHECK-V6-NEXT: bx lr31;32; CHECK-V7-LABEL: test3:33; CHECK-V7: @ %bb.0:34; CHECK-V7-NEXT: ubfx r0, r0, #8, #1635; CHECK-V7-NEXT: bx lr36 %B.u = lshr i32 %A.u, 837 %C.u = shl i32 %A.u, 2438 %D.u = or i32 %B.u, %C.u39 %E.u = trunc i32 %D.u to i1640 %F.u = zext i16 %E.u to i3241 ret i32 %F.u42}43 44define zeroext i32 @test4(i32 %A.u) {45; CHECK-V6-LABEL: test4:46; CHECK-V6: @ %bb.0:47; CHECK-V6-NEXT: lsr r0, r0, #848; CHECK-V6-NEXT: uxtb r0, r049; CHECK-V6-NEXT: bx lr50;51; CHECK-V7-LABEL: test4:52; CHECK-V7: @ %bb.0:53; CHECK-V7-NEXT: ubfx r0, r0, #8, #854; CHECK-V7-NEXT: bx lr55 %B.u = lshr i32 %A.u, 856 %C.u = shl i32 %A.u, 2457 %D.u = or i32 %B.u, %C.u58 %E.u = trunc i32 %D.u to i859 %F.u = zext i8 %E.u to i3260 ret i32 %F.u61}62 63define zeroext i16 @test5(i32 %A.u) {64; CHECK-LABEL: test5:65; CHECK: @ %bb.0:66; CHECK-NEXT: uxth r0, r067; CHECK-NEXT: bx lr68 %B.u = trunc i32 %A.u to i1669 ret i16 %B.u70}71 72define zeroext i32 @test6(i32 %A.u, i32 %B.u) {73; CHECK-LABEL: test6:74; CHECK: @ %bb.0:75; CHECK-NEXT: uxtah r0, r0, r176; CHECK-NEXT: bx lr77 %C.u = trunc i32 %B.u to i1678 %D.u = zext i16 %C.u to i3279 %E.u = add i32 %A.u, %D.u80 ret i32 %E.u81}82 83define zeroext i32 @test7(i32 %A, i32 %X) {84; CHECK-LABEL: test7:85; CHECK: @ %bb.0:86; CHECK-NEXT: uxtab r0, r1, r0, ror #887; CHECK-NEXT: bx lr88 %B = lshr i32 %A, 889 %C = shl i32 %A, 2490 %D = or i32 %B, %C91 %E = trunc i32 %D to i892 %F = zext i8 %E to i3293 %G = add i32 %F, %X94 ret i32 %G95}96 97define zeroext i32 @test8(i32 %A, i32 %X) {98; CHECK-LABEL: test8:99; CHECK: @ %bb.0:100; CHECK-NEXT: uxtab r0, r1, r0, ror #16101; CHECK-NEXT: bx lr102 %B = lshr i32 %A, 16103 %C = shl i32 %A, 16104 %D = or i32 %B, %C105 %E = trunc i32 %D to i8106 %F = zext i8 %E to i32107 %G = add i32 %F, %X108 ret i32 %G109}110 111define zeroext i32 @test9(i32 %A, i32 %X) {112; CHECK-LABEL: test9:113; CHECK: @ %bb.0:114; CHECK-NEXT: uxtah r0, r1, r0, ror #8115; CHECK-NEXT: bx lr116 %B = lshr i32 %A, 8117 %C = shl i32 %A, 24118 %D = or i32 %B, %C119 %E = trunc i32 %D to i16120 %F = zext i16 %E to i32121 %G = add i32 %F, %X122 ret i32 %G123}124 125define zeroext i32 @test10(i32 %A, i32 %X) {126; CHECK-LABEL: test10:127; CHECK: @ %bb.0:128; CHECK-NEXT: uxtah r0, r1, r0, ror #24129; CHECK-NEXT: bx lr130 %B = lshr i32 %A, 24131 %C = shl i32 %A, 8132 %D = or i32 %B, %C133 %E = trunc i32 %D to i16134 %F = zext i16 %E to i32135 %G = add i32 %F, %X136 ret i32 %G137}138 139define zeroext i32 @test11(i32 %A, i32 %X) {140; CHECK-LABEL: test11:141; CHECK: @ %bb.0:142; CHECK-NEXT: uxtab r0, r1, r0143; CHECK-NEXT: bx lr144 %B = and i32 %A, 255145 %add = add i32 %X, %B146 ret i32 %add147}148 149define zeroext i32 @test12(i32 %A, i32 %X) {150; CHECK-LABEL: test12:151; CHECK: @ %bb.0:152; CHECK-NEXT: uxtab r0, r1, r0, ror #8153; CHECK-NEXT: bx lr154 %B = lshr i32 %A, 8155 %and = and i32 %B, 255156 %add = add i32 %and, %X157 ret i32 %add158}159 160define zeroext i32 @test13(i32 %A, i32 %X) {161; CHECK-LABEL: test13:162; CHECK: @ %bb.0:163; CHECK-NEXT: uxtab r0, r1, r0, ror #16164; CHECK-NEXT: bx lr165 %B = lshr i32 %A, 16166 %and = and i32 %B, 255167 %add = add i32 %and, %X168 ret i32 %add169}170 171define zeroext i32 @test14(i32 %A, i32 %X) {172; CHECK-LABEL: test14:173; CHECK: @ %bb.0:174; CHECK-NEXT: uxtah r0, r1, r0175; CHECK-NEXT: bx lr176 %B = and i32 %A, 65535177 %add = add i32 %X, %B178 ret i32 %add179}180 181define zeroext i32 @test15(i32 %A, i32 %X) {182; CHECK-LABEL: test15:183; CHECK: @ %bb.0:184; CHECK-NEXT: uxtah r0, r1, r0, ror #8185; CHECK-NEXT: bx lr186 %B = lshr i32 %A, 8187 %and = and i32 %B, 65535188 %add = add i32 %and, %X189 ret i32 %add190}191 192define zeroext i32 @test16(i32 %A, i32 %X) {193; CHECK-LABEL: test16:194; CHECK: @ %bb.0:195; CHECK-NEXT: uxtah r0, r1, r0, ror #24196; CHECK-NEXT: bx lr197 %B = lshr i32 %A, 24198 %C = shl i32 %A, 8199 %D = or i32 %B, %C200 %E = and i32 %D, 65535201 %F = add i32 %E, %X202 ret i32 %F203}204