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1# RUN: llc -run-pass=arm-cp-islands -o - %s | FileCheck %s2 3# Test created by tweaking the register allocation after stopping the IR below4# just before constant islands. We were forwarding the table index to the end of5# the block, even though the LEA clobbered it.6 7# CHECK-LABEL: name: foo8# CHECK: tBR_JT9 # This order is important. If the jump-table comes first then the10 # transformation is valid because the LEA can be removed, see second test.11# CHECK: CONSTPOOL_ENTRY12# CHECK: JUMPTABLE_ADDRS13 14# CHECK-LABEL: name: bar15# CHECK: tTBB_JT $pc, killed $r116 17--- |18 ; ModuleID = 'simple.ll'19 source_filename = "simple.ll"20 target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"21 target triple = "thumbv6m-none--eabi"22 23 define void @foo(i8 %in, ptr %addr) {24 store i32 12345678, ptr %addr25 %1 = call i32 @llvm.arm.space(i32 980, i32 undef)26 %2 = zext i8 %in to i3227 switch i32 %2, label %default [28 i32 0, label %d129 i32 1, label %d230 i32 3, label %d331 i32 4, label %d432 i32 5, label %d533 i32 6, label %d634 i32 7, label %d735 i32 2, label %d836 i32 8, label %d937 i32 9, label %d1038 i32 19, label %d1139 i32 20, label %d1240 i32 21, label %d1341 i32 22, label %d1442 i32 24, label %d1543 i32 25, label %d1644 i32 26, label %d1745 ]46 47 default: ; preds = %048 unreachable49 50 d1: ; preds = %051 unreachable52 53 d2: ; preds = %054 unreachable55 56 d3: ; preds = %057 unreachable58 59 d4: ; preds = %060 unreachable61 62 d5: ; preds = %063 unreachable64 65 d6: ; preds = %066 unreachable67 68 d7: ; preds = %069 unreachable70 71 d8: ; preds = %072 unreachable73 74 d9: ; preds = %075 unreachable76 77 d10: ; preds = %078 unreachable79 80 d11: ; preds = %081 unreachable82 83 d12: ; preds = %084 unreachable85 86 d13: ; preds = %087 unreachable88 89 d14: ; preds = %090 unreachable91 92 d15: ; preds = %093 unreachable94 95 d16: ; preds = %096 unreachable97 98 d17: ; preds = %099 unreachable100 }101 102 define void @bar(i8 %in, ptr %addr) {103 store i32 12345678, ptr %addr104 %1 = zext i8 %in to i32105 switch i32 %1, label %default [106 i32 0, label %d1107 i32 1, label %d2108 i32 3, label %d3109 i32 4, label %d4110 i32 5, label %d5111 i32 6, label %d6112 i32 7, label %d7113 i32 2, label %d8114 i32 8, label %d9115 i32 9, label %d10116 i32 19, label %d11117 i32 20, label %d12118 i32 21, label %d13119 i32 22, label %d14120 i32 24, label %d15121 i32 25, label %d16122 i32 26, label %d17123 ]124 125 default: ; preds = %0126 unreachable127 128 d1: ; preds = %0129 unreachable130 131 d2: ; preds = %0132 unreachable133 134 d3: ; preds = %0135 unreachable136 137 d4: ; preds = %0138 unreachable139 140 d5: ; preds = %0141 unreachable142 143 d6: ; preds = %0144 unreachable145 146 d7: ; preds = %0147 unreachable148 149 d8: ; preds = %0150 unreachable151 152 d9: ; preds = %0153 unreachable154 155 d10: ; preds = %0156 unreachable157 158 d11: ; preds = %0159 unreachable160 161 d12: ; preds = %0162 unreachable163 164 d13: ; preds = %0165 unreachable166 167 d14: ; preds = %0168 unreachable169 170 d15: ; preds = %0171 unreachable172 173 d16: ; preds = %0174 unreachable175 176 d17: ; preds = %0177 unreachable178 }179 180 ; Function Attrs: nounwind181 declare i32 @llvm.arm.space(i32, i32) #0182 183 ; Function Attrs: nounwind184 declare void @llvm.stackprotector(ptr, ptr) #0185 186 attributes #0 = { nounwind }187 188...189---190name: foo191alignment: 2192exposesReturnsTwice: false193legalized: false194regBankSelected: false195selected: false196tracksRegLiveness: true197liveins: 198 - { reg: '$r0' }199 - { reg: '$r1' }200frameInfo: 201 isFrameAddressTaken: false202 isReturnAddressTaken: false203 hasStackMap: false204 hasPatchPoint: false205 stackSize: 0206 offsetAdjustment: 0207 maxAlignment: 0208 adjustsStack: false209 hasCalls: false210 maxCallFrameSize: 0211 hasOpaqueSPAdjustment: false212 hasVAStart: false213 hasMustTailInVarArgFunc: false214constants: 215 - id: 0216 value: i32 12345678217 alignment: 4218jumpTable: 219 kind: inline220 entries: 221 - id: 0222 blocks: [ '%bb.3.d2', '%bb.9.d8', '%bb.4.d3', '%bb.5.d4', 223 '%bb.6.d5', '%bb.7.d6', '%bb.8.d7', '%bb.10.d9', 224 '%bb.11.d10', '%bb.2.d1', '%bb.2.d1', '%bb.2.d1', 225 '%bb.2.d1', '%bb.2.d1', '%bb.2.d1', '%bb.2.d1', 226 '%bb.2.d1', '%bb.2.d1', '%bb.12.d11', '%bb.13.d12', 227 '%bb.14.d13', '%bb.15.d14', '%bb.2.d1', '%bb.16.d15', 228 '%bb.17.d16', '%bb.18.d17' ]229body: |230 bb.0 (%ir-block.0):231 successors: %bb.2.d1(0x03c3c3c4), %bb.1(0x7c3c3c3c)232 liveins: $r0, $r1233 234 $r2 = tLDRpci %const.0, 14, $noreg235 tSTRi killed $r2, killed $r1, 0, 14, $noreg :: (store (s32) into %ir.addr)236 dead $r1 = SPACE 980, undef $r0237 $r0 = tUXTB killed $r0, 14, $noreg238 $r1, dead $cpsr = tSUBi3 killed $r0, 1, 14, $noreg239 tCMPi8 $r1, 25, 14, $noreg, implicit-def $cpsr240 tBcc %bb.2.d1, 8, killed $cpsr241 242 bb.1 (%ir-block.0):243 successors: %bb.3.d2(0x07c549d2), %bb.9.d8(0x07c549d2), %bb.4.d3(0x07c549d2), %bb.5.d4(0x07c549d2), %bb.6.d5(0x07c549d2), %bb.7.d6(0x07c549d2), %bb.8.d7(0x07c549d2), %bb.10.d9(0x07c549d2), %bb.11.d10(0x07c549d2), %bb.2.d1(0x03ab62db), %bb.12.d11(0x07c549d2), %bb.13.d12(0x07c549d2), %bb.14.d13(0x07c549d2), %bb.15.d14(0x07c549d2), %bb.16.d15(0x07c549d2), %bb.17.d16(0x07c549d2), %bb.18.d17(0x07c549d2)244 liveins: $r1245 246 $r0, dead $cpsr = tLSLri killed $r1, 2, 14, $noreg247 $r1 = tLEApcrelJT %jump-table.0, 14, $noreg248 $r0 = tLDRr killed $r1, killed $r0, 14, $noreg :: (load (s32) from jump-table)249 tBR_JTr killed $r0, %jump-table.0250 251 bb.3.d2:252 253 bb.9.d8:254 255 bb.4.d3:256 257 bb.5.d4:258 259 bb.6.d5:260 261 bb.7.d6:262 263 bb.8.d7:264 265 bb.10.d9:266 267 bb.11.d10:268 269 bb.2.d1:270 271 bb.12.d11:272 273 bb.13.d12:274 275 bb.14.d13:276 277 bb.15.d14:278 279 bb.16.d15:280 281 bb.17.d16:282 283 bb.18.d17:284 285...286 287---288name: bar289alignment: 2290exposesReturnsTwice: false291legalized: false292regBankSelected: false293selected: false294tracksRegLiveness: true295liveins: 296 - { reg: '$r0' }297 - { reg: '$r1' }298frameInfo: 299 isFrameAddressTaken: false300 isReturnAddressTaken: false301 hasStackMap: false302 hasPatchPoint: false303 stackSize: 0304 offsetAdjustment: 0305 maxAlignment: 0306 adjustsStack: false307 hasCalls: false308 maxCallFrameSize: 0309 hasOpaqueSPAdjustment: false310 hasVAStart: false311 hasMustTailInVarArgFunc: false312constants: 313 - id: 0314 value: i32 12345678315 alignment: 4316jumpTable: 317 kind: inline318 entries: 319 - id: 0320 blocks: [ '%bb.3.d2', '%bb.9.d8', '%bb.4.d3', '%bb.5.d4', 321 '%bb.6.d5', '%bb.7.d6', '%bb.8.d7', '%bb.10.d9', 322 '%bb.11.d10', '%bb.2.d1', '%bb.2.d1', '%bb.2.d1', 323 '%bb.2.d1', '%bb.2.d1', '%bb.2.d1', '%bb.2.d1', 324 '%bb.2.d1', '%bb.2.d1', '%bb.12.d11', '%bb.13.d12', 325 '%bb.14.d13', '%bb.15.d14', '%bb.2.d1', '%bb.16.d15', 326 '%bb.17.d16', '%bb.18.d17' ]327body: |328 bb.0 (%ir-block.0):329 successors: %bb.2.d1(0x03c3c3c4), %bb.1(0x7c3c3c3c)330 liveins: $r0, $r1331 332 $r2 = tLDRpci %const.0, 14, $noreg333 tSTRi killed $r2, killed $r1, 0, 14, $noreg :: (store (s32) into %ir.addr)334 $r0 = tUXTB killed $r0, 14, $noreg335 $r1, dead $cpsr = tSUBi3 killed $r0, 1, 14, $noreg336 tCMPi8 $r1, 25, 14, $noreg, implicit-def $cpsr337 tBcc %bb.2.d1, 8, killed $cpsr338 339 bb.1 (%ir-block.0):340 successors: %bb.3.d2(0x07c549d2), %bb.9.d8(0x07c549d2), %bb.4.d3(0x07c549d2), %bb.5.d4(0x07c549d2), %bb.6.d5(0x07c549d2), %bb.7.d6(0x07c549d2), %bb.8.d7(0x07c549d2), %bb.10.d9(0x07c549d2), %bb.11.d10(0x07c549d2), %bb.2.d1(0x03ab62db), %bb.12.d11(0x07c549d2), %bb.13.d12(0x07c549d2), %bb.14.d13(0x07c549d2), %bb.15.d14(0x07c549d2), %bb.16.d15(0x07c549d2), %bb.17.d16(0x07c549d2), %bb.18.d17(0x07c549d2)341 liveins: $r1342 343 $r0, dead $cpsr = tLSLri killed $r1, 2, 14, $noreg344 $r1 = tLEApcrelJT %jump-table.0, 14, $noreg345 $r0 = tLDRr killed $r1, killed $r0, 14, $noreg :: (load (s32) from jump-table)346 tBR_JTr killed $r0, %jump-table.0347 348 bb.3.d2:349 350 bb.9.d8:351 352 bb.4.d3:353 354 bb.5.d4:355 356 bb.6.d5:357 358 bb.7.d6:359 360 bb.8.d7:361 362 bb.10.d9:363 364 bb.11.d10:365 366 bb.2.d1:367 368 bb.12.d11:369 370 bb.13.d12:371 372 bb.14.d13:373 374 bb.15.d14:375 376 bb.16.d15:377 378 bb.17.d16:379 380 bb.18.d17:381 382...383