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1; RUN: llc -mtriple=thumbv7k-apple-watchos2.0 -o - %s | FileCheck %s2 3%struct = type { i8, i64, i8, double, i8, <2 x float>, i8, <4 x float> }4 5define i32 @test_i64_align() "frame-pointer"="all" {6; CHECK-LABEL: test_i64_align:7; CHECK: movs r0, #88 ret i32 ptrtoint(ptr getelementptr(%struct, ptr null, i32 0, i32 1) to i32)9}10 11define i32 @test_f64_align() "frame-pointer"="all" {12; CHECK-LABEL: test_f64_align:13; CHECK: movs r0, #2414 ret i32 ptrtoint(ptr getelementptr(%struct, ptr null, i32 0, i32 3) to i32)15}16 17define i32 @test_v2f32_align() "frame-pointer"="all" {18; CHECK-LABEL: test_v2f32_align:19; CHECK: movs r0, #4020 ret i32 ptrtoint(ptr getelementptr(%struct, ptr null, i32 0, i32 5) to i32)21}22 23define i32 @test_v4f32_align() "frame-pointer"="all" {24; CHECK-LABEL: test_v4f32_align:25; CHECK: movs r0, #6426 ret i32 ptrtoint(ptr getelementptr(%struct, ptr null, i32 0, i32 7) to i32)27}28 29; Key point here is than an extra register has to be saved so that the DPRs end30; up in an aligned location (as prologue/epilogue inserter had calculated).31define void @test_dpr_unwind_align() "frame-pointer"="all" {32; CHECK-LABEL: test_dpr_unwind_align:33; CHECK: push {r5, r6, r7, lr}34; CHECK-NOT: sub sp35; CHECK: vpush {d8, d9}36; CHECK: .cfi_offset d9, -2437; CHECK: .cfi_offset d8, -3238; [...]39; CHECK: bl _test_i64_align40; CHECK-NOT: add sp,41; CHECK: vpop {d8, d9}42; CHECK-NOT: add sp,43; CHECK: pop {r5, r6, r7, pc}44 45 call void asm sideeffect "", "~{r6},~{d8},~{d9}"()46 47 ; Whatever48 call i32 @test_i64_align()49 ret void50}51 52; This time, there's no viable way to tack CS-registers onto the list: a real SP53; adjustment needs to be performed to put d8 and d9 where they should be.54define void @test_dpr_unwind_align_manually() "frame-pointer"="all" {55; CHECK-LABEL: test_dpr_unwind_align_manually:56; CHECK: push {r4, r5, r6, r7, lr}57; CHECK-NOT: sub sp58; CHECK: push.w {r8, r11}59; CHECK: sub sp, #460; CHECK: vpush {d8, d9}61; CHECK: .cfi_offset d9, -4062; CHECK: .cfi_offset d8, -4863; [...]64; CHECK: bl _test_i64_align65; CHECK-NOT: add sp,66; CHECK: vpop {d8, d9}67; CHECK: add sp, #468; CHECK: pop.w {r8, r11}69; CHECK: pop {r4, r5, r6, r7, pc}70 71 call void asm sideeffect "", "~{r4},~{r5},~{r6},~{r7},~{r8},~{d8},~{d9}"()72 73 ; Whatever74 call i32 @test_i64_align()75 ret void76}77 78; If there's only a CS1 area, the sub should be in the right place:79define void @test_dpr_unwind_align_just_cs1() "frame-pointer"="all" {80; CHECK-LABEL: test_dpr_unwind_align_just_cs1:81; CHECK: push {r4, r5, r6, r7, lr}82; CHECK: sub sp, #483; CHECK: vpush {d8, d9}84; CHECK: .cfi_offset d9, -3285; CHECK: .cfi_offset d8, -4086; CHECK: sub sp, #887; [...]88; CHECK: bl _test_i64_align89; CHECK: add sp, #890; CHECK: vpop {d8, d9}91; CHECK: add sp, #492; CHECK: pop {r4, r5, r6, r7, pc}93 94 call void asm sideeffect "", "~{r4},~{r5},~{r6},~{r7},~{d8},~{d9}"()95 96 ; Whatever97 call i32 @test_i64_align()98 ret void99}100 101; If there are no DPRs, we shouldn't try to align the stack in stages anyway102define void @test_dpr_unwind_align_no_dprs() "frame-pointer"="all" {103; CHECK-LABEL: test_dpr_unwind_align_no_dprs:104; CHECK: push {r4, r5, r6, r7, lr}105; CHECK: sub sp, #12106; [...]107; CHECK: bl _test_i64_align108; CHECK: add sp, #12109; CHECK: pop {r4, r5, r6, r7, pc}110 111 call void asm sideeffect "", "~{r4},~{r5},~{r6},~{r7}"()112 113 ; Whatever114 call i32 @test_i64_align()115 ret void116}117 118; 128-bit vectors should use 128-bit (i.e. correctly aligned) slots on119; the stack.120define <4 x float> @test_v128_stack_pass([8 x double], float, <4 x float> %in) "frame-pointer"="none" {121; CHECK-LABEL: test_v128_stack_pass:122; CHECK: add r[[ADDR:[0-9]+]], sp, #16123; CHECK: vld1.64 {d0, d1}, [r[[ADDR]]:128]124 125 ret <4 x float> %in126}127 128declare void @varargs(i32, ...)129 130; When varargs are enabled, we go down a different route. Still want 128-bit131; alignment though.132define void @test_v128_stack_pass_varargs(<4 x float> %in) "frame-pointer"="all" {133; CHECK-LABEL: test_v128_stack_pass_varargs:134; CHECK: add r[[ADDR:[0-9]+]], sp, #16135; CHECK: vst1.64 {d0, d1}, [r[[ADDR]]:128]136 137 call void(i32, ...) @varargs(i32 undef, [3 x i32] undef, float undef, <4 x float> %in)138 ret void139}140 141; To be compatible with AAPCS's va_start model (store r0-r3 at incoming SP, give142; a single pointer), 64-bit quantities must be pass143define i64 @test_64bit_gpr_align(i32, i64 %r2_r3, i32 %sp) "frame-pointer"="none" {144; CHECK-LABEL: test_64bit_gpr_align:145; CHECK: ldr [[RHS:r[0-9]+]], [sp]146; CHECK: adds r0, [[RHS]], r2147; CHECK: adc r1, r3, #0148 149 %ext = zext i32 %sp to i64150 %sum = add i64 %ext, %r2_r3151 ret i64 %sum152}153