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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=armv7-none-linux-gnueabi -pre-RA-sched=source | FileCheck %s3; Test that we correctly align elements when using va_arg4 5define i64 @test1(i32 %i, ...) nounwind optsize {6; CHECK-LABEL: test1:7; CHECK: @ %bb.0: @ %entry8; CHECK-NEXT: .pad #169; CHECK-NEXT: sub sp, sp, #1610; CHECK-NEXT: add r0, sp, #411; CHECK-NEXT: stmib sp, {r1, r2, r3}12; CHECK-NEXT: add r0, r0, #713; CHECK-NEXT: bic r1, r0, #714; CHECK-NEXT: orr r0, r1, #415; CHECK-NEXT: str r0, [sp]16; CHECK-NEXT: ldr r0, [r1]17; CHECK-NEXT: add r2, r1, #818; CHECK-NEXT: str r2, [sp]19; CHECK-NEXT: ldr r1, [r1, #4]20; CHECK-NEXT: add sp, sp, #1621; CHECK-NEXT: bx lr22entry:23 %g = alloca ptr, align 424 call void @llvm.va_start(ptr %g)25 %0 = va_arg ptr %g, i6426 call void @llvm.va_end(ptr %g)27 ret i64 %028}29 30define double @test2(i32 %a, ptr %b, ...) nounwind optsize {31; CHECK-LABEL: test2:32; CHECK: @ %bb.0: @ %entry33; CHECK-NEXT: .pad #1234; CHECK-NEXT: sub sp, sp, #1235; CHECK-NEXT: add r0, sp, #436; CHECK-NEXT: stmib sp, {r2, r3}37; CHECK-NEXT: add r0, r0, #1138; CHECK-NEXT: bic r0, r0, #339; CHECK-NEXT: str r2, [r1]40; CHECK-NEXT: add r1, r0, #841; CHECK-NEXT: str r1, [sp]42; CHECK-NEXT: vldr d16, [r0]43; CHECK-NEXT: vmov r0, r1, d1644; CHECK-NEXT: add sp, sp, #1245; CHECK-NEXT: bx lr46entry:47 %ap = alloca ptr, align 4 ; <ptr> [#uses=3]48 call void @llvm.va_start(ptr %ap)49 %0 = va_arg ptr %ap, i32 ; <i32> [#uses=0]50 store i32 %0, ptr %b51 %1 = va_arg ptr %ap, double ; <double> [#uses=1]52 call void @llvm.va_end(ptr %ap)53 ret double %154}55 56 57declare void @llvm.va_start(ptr) nounwind58 59declare void @llvm.va_end(ptr) nounwind60