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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc -mtriple=armv7a-eabihf -mattr=+neon %s -o - | FileCheck %s3 4define <8 x i8> @vabas8(ptr %A, ptr %B, ptr %C) nounwind {5; CHECK-LABEL: vabas8:6; CHECK: @ %bb.0:7; CHECK-NEXT: vldr d16, [r2]8; CHECK-NEXT: vldr d17, [r1]9; CHECK-NEXT: vldr d0, [r0]10; CHECK-NEXT: vaba.s8 d0, d17, d1611; CHECK-NEXT: bx lr12 %tmp1 = load <8 x i8>, ptr %A13 %tmp2 = load <8 x i8>, ptr %B14 %tmp3 = load <8 x i8>, ptr %C15 %tmp4 = call <8 x i8> @llvm.arm.neon.vabds.v8i8(<8 x i8> %tmp2, <8 x i8> %tmp3)16 %tmp5 = add <8 x i8> %tmp1, %tmp417 ret <8 x i8> %tmp518}19 20define <4 x i16> @vabas16(ptr %A, ptr %B, ptr %C) nounwind {21; CHECK-LABEL: vabas16:22; CHECK: @ %bb.0:23; CHECK-NEXT: vldr d16, [r2]24; CHECK-NEXT: vldr d17, [r1]25; CHECK-NEXT: vldr d0, [r0]26; CHECK-NEXT: vaba.s16 d0, d17, d1627; CHECK-NEXT: bx lr28 %tmp1 = load <4 x i16>, ptr %A29 %tmp2 = load <4 x i16>, ptr %B30 %tmp3 = load <4 x i16>, ptr %C31 %tmp4 = call <4 x i16> @llvm.arm.neon.vabds.v4i16(<4 x i16> %tmp2, <4 x i16> %tmp3)32 %tmp5 = add <4 x i16> %tmp1, %tmp433 ret <4 x i16> %tmp534}35 36define <2 x i32> @vabas32(ptr %A, ptr %B, ptr %C) nounwind {37; CHECK-LABEL: vabas32:38; CHECK: @ %bb.0:39; CHECK-NEXT: vldr d16, [r2]40; CHECK-NEXT: vldr d17, [r1]41; CHECK-NEXT: vldr d0, [r0]42; CHECK-NEXT: vaba.s32 d0, d17, d1643; CHECK-NEXT: bx lr44 %tmp1 = load <2 x i32>, ptr %A45 %tmp2 = load <2 x i32>, ptr %B46 %tmp3 = load <2 x i32>, ptr %C47 %tmp4 = call <2 x i32> @llvm.arm.neon.vabds.v2i32(<2 x i32> %tmp2, <2 x i32> %tmp3)48 %tmp5 = add <2 x i32> %tmp1, %tmp449 ret <2 x i32> %tmp550}51 52define <8 x i8> @vabau8(ptr %A, ptr %B, ptr %C) nounwind {53; CHECK-LABEL: vabau8:54; CHECK: @ %bb.0:55; CHECK-NEXT: vldr d16, [r2]56; CHECK-NEXT: vldr d17, [r1]57; CHECK-NEXT: vldr d0, [r0]58; CHECK-NEXT: vaba.u8 d0, d17, d1659; CHECK-NEXT: bx lr60 %tmp1 = load <8 x i8>, ptr %A61 %tmp2 = load <8 x i8>, ptr %B62 %tmp3 = load <8 x i8>, ptr %C63 %tmp4 = call <8 x i8> @llvm.arm.neon.vabdu.v8i8(<8 x i8> %tmp2, <8 x i8> %tmp3)64 %tmp5 = add <8 x i8> %tmp1, %tmp465 ret <8 x i8> %tmp566}67 68define <4 x i16> @vabau16(ptr %A, ptr %B, ptr %C) nounwind {69; CHECK-LABEL: vabau16:70; CHECK: @ %bb.0:71; CHECK-NEXT: vldr d16, [r2]72; CHECK-NEXT: vldr d17, [r1]73; CHECK-NEXT: vldr d0, [r0]74; CHECK-NEXT: vaba.u16 d0, d17, d1675; CHECK-NEXT: bx lr76 %tmp1 = load <4 x i16>, ptr %A77 %tmp2 = load <4 x i16>, ptr %B78 %tmp3 = load <4 x i16>, ptr %C79 %tmp4 = call <4 x i16> @llvm.arm.neon.vabdu.v4i16(<4 x i16> %tmp2, <4 x i16> %tmp3)80 %tmp5 = add <4 x i16> %tmp1, %tmp481 ret <4 x i16> %tmp582}83 84define <2 x i32> @vabau32(ptr %A, ptr %B, ptr %C) nounwind {85; CHECK-LABEL: vabau32:86; CHECK: @ %bb.0:87; CHECK-NEXT: vldr d16, [r2]88; CHECK-NEXT: vldr d17, [r1]89; CHECK-NEXT: vldr d0, [r0]90; CHECK-NEXT: vaba.u32 d0, d17, d1691; CHECK-NEXT: bx lr92 %tmp1 = load <2 x i32>, ptr %A93 %tmp2 = load <2 x i32>, ptr %B94 %tmp3 = load <2 x i32>, ptr %C95 %tmp4 = call <2 x i32> @llvm.arm.neon.vabdu.v2i32(<2 x i32> %tmp2, <2 x i32> %tmp3)96 %tmp5 = add <2 x i32> %tmp1, %tmp497 ret <2 x i32> %tmp598}99 100define <16 x i8> @vabaQs8(ptr %A, ptr %B, ptr %C) nounwind {101; CHECK-LABEL: vabaQs8:102; CHECK: @ %bb.0:103; CHECK-NEXT: vld1.64 {d16, d17}, [r2]104; CHECK-NEXT: vld1.64 {d18, d19}, [r1]105; CHECK-NEXT: vld1.64 {d0, d1}, [r0]106; CHECK-NEXT: vaba.s8 q0, q9, q8107; CHECK-NEXT: bx lr108 %tmp1 = load <16 x i8>, ptr %A109 %tmp2 = load <16 x i8>, ptr %B110 %tmp3 = load <16 x i8>, ptr %C111 %tmp4 = call <16 x i8> @llvm.arm.neon.vabds.v16i8(<16 x i8> %tmp2, <16 x i8> %tmp3)112 %tmp5 = add <16 x i8> %tmp1, %tmp4113 ret <16 x i8> %tmp5114}115 116define <8 x i16> @vabaQs16(ptr %A, ptr %B, ptr %C) nounwind {117; CHECK-LABEL: vabaQs16:118; CHECK: @ %bb.0:119; CHECK-NEXT: vld1.64 {d16, d17}, [r2]120; CHECK-NEXT: vld1.64 {d18, d19}, [r1]121; CHECK-NEXT: vld1.64 {d0, d1}, [r0]122; CHECK-NEXT: vaba.s16 q0, q9, q8123; CHECK-NEXT: bx lr124 %tmp1 = load <8 x i16>, ptr %A125 %tmp2 = load <8 x i16>, ptr %B126 %tmp3 = load <8 x i16>, ptr %C127 %tmp4 = call <8 x i16> @llvm.arm.neon.vabds.v8i16(<8 x i16> %tmp2, <8 x i16> %tmp3)128 %tmp5 = add <8 x i16> %tmp1, %tmp4129 ret <8 x i16> %tmp5130}131 132define <4 x i32> @vabaQs32(ptr %A, ptr %B, ptr %C) nounwind {133; CHECK-LABEL: vabaQs32:134; CHECK: @ %bb.0:135; CHECK-NEXT: vld1.64 {d16, d17}, [r2]136; CHECK-NEXT: vld1.64 {d18, d19}, [r1]137; CHECK-NEXT: vld1.64 {d0, d1}, [r0]138; CHECK-NEXT: vaba.s32 q0, q9, q8139; CHECK-NEXT: bx lr140 %tmp1 = load <4 x i32>, ptr %A141 %tmp2 = load <4 x i32>, ptr %B142 %tmp3 = load <4 x i32>, ptr %C143 %tmp4 = call <4 x i32> @llvm.arm.neon.vabds.v4i32(<4 x i32> %tmp2, <4 x i32> %tmp3)144 %tmp5 = add <4 x i32> %tmp1, %tmp4145 ret <4 x i32> %tmp5146}147 148define <16 x i8> @vabaQu8(ptr %A, ptr %B, ptr %C) nounwind {149; CHECK-LABEL: vabaQu8:150; CHECK: @ %bb.0:151; CHECK-NEXT: vld1.64 {d16, d17}, [r2]152; CHECK-NEXT: vld1.64 {d18, d19}, [r1]153; CHECK-NEXT: vld1.64 {d0, d1}, [r0]154; CHECK-NEXT: vaba.u8 q0, q9, q8155; CHECK-NEXT: bx lr156 %tmp1 = load <16 x i8>, ptr %A157 %tmp2 = load <16 x i8>, ptr %B158 %tmp3 = load <16 x i8>, ptr %C159 %tmp4 = call <16 x i8> @llvm.arm.neon.vabdu.v16i8(<16 x i8> %tmp2, <16 x i8> %tmp3)160 %tmp5 = add <16 x i8> %tmp1, %tmp4161 ret <16 x i8> %tmp5162}163 164define <8 x i16> @vabaQu16(ptr %A, ptr %B, ptr %C) nounwind {165; CHECK-LABEL: vabaQu16:166; CHECK: @ %bb.0:167; CHECK-NEXT: vld1.64 {d16, d17}, [r2]168; CHECK-NEXT: vld1.64 {d18, d19}, [r1]169; CHECK-NEXT: vld1.64 {d0, d1}, [r0]170; CHECK-NEXT: vaba.u16 q0, q9, q8171; CHECK-NEXT: bx lr172 %tmp1 = load <8 x i16>, ptr %A173 %tmp2 = load <8 x i16>, ptr %B174 %tmp3 = load <8 x i16>, ptr %C175 %tmp4 = call <8 x i16> @llvm.arm.neon.vabdu.v8i16(<8 x i16> %tmp2, <8 x i16> %tmp3)176 %tmp5 = add <8 x i16> %tmp1, %tmp4177 ret <8 x i16> %tmp5178}179 180define <4 x i32> @vabaQu32(ptr %A, ptr %B, ptr %C) nounwind {181; CHECK-LABEL: vabaQu32:182; CHECK: @ %bb.0:183; CHECK-NEXT: vld1.64 {d16, d17}, [r2]184; CHECK-NEXT: vld1.64 {d18, d19}, [r1]185; CHECK-NEXT: vld1.64 {d0, d1}, [r0]186; CHECK-NEXT: vaba.u32 q0, q9, q8187; CHECK-NEXT: bx lr188 %tmp1 = load <4 x i32>, ptr %A189 %tmp2 = load <4 x i32>, ptr %B190 %tmp3 = load <4 x i32>, ptr %C191 %tmp4 = call <4 x i32> @llvm.arm.neon.vabdu.v4i32(<4 x i32> %tmp2, <4 x i32> %tmp3)192 %tmp5 = add <4 x i32> %tmp1, %tmp4193 ret <4 x i32> %tmp5194}195 196declare <8 x i8> @llvm.arm.neon.vabds.v8i8(<8 x i8>, <8 x i8>) nounwind readnone197declare <4 x i16> @llvm.arm.neon.vabds.v4i16(<4 x i16>, <4 x i16>) nounwind readnone198declare <2 x i32> @llvm.arm.neon.vabds.v2i32(<2 x i32>, <2 x i32>) nounwind readnone199 200declare <8 x i8> @llvm.arm.neon.vabdu.v8i8(<8 x i8>, <8 x i8>) nounwind readnone201declare <4 x i16> @llvm.arm.neon.vabdu.v4i16(<4 x i16>, <4 x i16>) nounwind readnone202declare <2 x i32> @llvm.arm.neon.vabdu.v2i32(<2 x i32>, <2 x i32>) nounwind readnone203 204declare <16 x i8> @llvm.arm.neon.vabds.v16i8(<16 x i8>, <16 x i8>) nounwind readnone205declare <8 x i16> @llvm.arm.neon.vabds.v8i16(<8 x i16>, <8 x i16>) nounwind readnone206declare <4 x i32> @llvm.arm.neon.vabds.v4i32(<4 x i32>, <4 x i32>) nounwind readnone207 208declare <16 x i8> @llvm.arm.neon.vabdu.v16i8(<16 x i8>, <16 x i8>) nounwind readnone209declare <8 x i16> @llvm.arm.neon.vabdu.v8i16(<8 x i16>, <8 x i16>) nounwind readnone210declare <4 x i32> @llvm.arm.neon.vabdu.v4i32(<4 x i32>, <4 x i32>) nounwind readnone211 212define <8 x i16> @vabals8(ptr %A, ptr %B, ptr %C) nounwind {213; CHECK-LABEL: vabals8:214; CHECK: @ %bb.0:215; CHECK-NEXT: vldr d16, [r2]216; CHECK-NEXT: vldr d17, [r1]217; CHECK-NEXT: vld1.64 {d0, d1}, [r0]218; CHECK-NEXT: vabal.s8 q0, d17, d16219; CHECK-NEXT: bx lr220 %tmp1 = load <8 x i16>, ptr %A221 %tmp2 = load <8 x i8>, ptr %B222 %tmp3 = load <8 x i8>, ptr %C223 %tmp4 = call <8 x i8> @llvm.arm.neon.vabds.v8i8(<8 x i8> %tmp2, <8 x i8> %tmp3)224 %tmp5 = zext <8 x i8> %tmp4 to <8 x i16>225 %tmp6 = add <8 x i16> %tmp1, %tmp5226 ret <8 x i16> %tmp6227}228 229define <4 x i32> @vabals16(ptr %A, ptr %B, ptr %C) nounwind {230; CHECK-LABEL: vabals16:231; CHECK: @ %bb.0:232; CHECK-NEXT: vldr d16, [r2]233; CHECK-NEXT: vldr d17, [r1]234; CHECK-NEXT: vld1.64 {d0, d1}, [r0]235; CHECK-NEXT: vabal.s16 q0, d17, d16236; CHECK-NEXT: bx lr237 %tmp1 = load <4 x i32>, ptr %A238 %tmp2 = load <4 x i16>, ptr %B239 %tmp3 = load <4 x i16>, ptr %C240 %tmp4 = call <4 x i16> @llvm.arm.neon.vabds.v4i16(<4 x i16> %tmp2, <4 x i16> %tmp3)241 %tmp5 = zext <4 x i16> %tmp4 to <4 x i32>242 %tmp6 = add <4 x i32> %tmp1, %tmp5243 ret <4 x i32> %tmp6244}245 246define <2 x i64> @vabals32(ptr %A, ptr %B, ptr %C) nounwind {247; CHECK-LABEL: vabals32:248; CHECK: @ %bb.0:249; CHECK-NEXT: vldr d16, [r2]250; CHECK-NEXT: vldr d17, [r1]251; CHECK-NEXT: vld1.64 {d0, d1}, [r0]252; CHECK-NEXT: vabal.s32 q0, d17, d16253; CHECK-NEXT: bx lr254 %tmp1 = load <2 x i64>, ptr %A255 %tmp2 = load <2 x i32>, ptr %B256 %tmp3 = load <2 x i32>, ptr %C257 %tmp4 = call <2 x i32> @llvm.arm.neon.vabds.v2i32(<2 x i32> %tmp2, <2 x i32> %tmp3)258 %tmp5 = zext <2 x i32> %tmp4 to <2 x i64>259 %tmp6 = add <2 x i64> %tmp1, %tmp5260 ret <2 x i64> %tmp6261}262 263define <8 x i16> @vabalu8(ptr %A, ptr %B, ptr %C) nounwind {264; CHECK-LABEL: vabalu8:265; CHECK: @ %bb.0:266; CHECK-NEXT: vldr d16, [r2]267; CHECK-NEXT: vldr d17, [r1]268; CHECK-NEXT: vld1.64 {d0, d1}, [r0]269; CHECK-NEXT: vabal.u8 q0, d17, d16270; CHECK-NEXT: bx lr271 %tmp1 = load <8 x i16>, ptr %A272 %tmp2 = load <8 x i8>, ptr %B273 %tmp3 = load <8 x i8>, ptr %C274 %tmp4 = call <8 x i8> @llvm.arm.neon.vabdu.v8i8(<8 x i8> %tmp2, <8 x i8> %tmp3)275 %tmp5 = zext <8 x i8> %tmp4 to <8 x i16>276 %tmp6 = add <8 x i16> %tmp1, %tmp5277 ret <8 x i16> %tmp6278}279 280define <4 x i32> @vabalu16(ptr %A, ptr %B, ptr %C) nounwind {281; CHECK-LABEL: vabalu16:282; CHECK: @ %bb.0:283; CHECK-NEXT: vldr d16, [r2]284; CHECK-NEXT: vldr d17, [r1]285; CHECK-NEXT: vld1.64 {d0, d1}, [r0]286; CHECK-NEXT: vabal.u16 q0, d17, d16287; CHECK-NEXT: bx lr288 %tmp1 = load <4 x i32>, ptr %A289 %tmp2 = load <4 x i16>, ptr %B290 %tmp3 = load <4 x i16>, ptr %C291 %tmp4 = call <4 x i16> @llvm.arm.neon.vabdu.v4i16(<4 x i16> %tmp2, <4 x i16> %tmp3)292 %tmp5 = zext <4 x i16> %tmp4 to <4 x i32>293 %tmp6 = add <4 x i32> %tmp1, %tmp5294 ret <4 x i32> %tmp6295}296 297define <2 x i64> @vabalu32(ptr %A, ptr %B, ptr %C) nounwind {298; CHECK-LABEL: vabalu32:299; CHECK: @ %bb.0:300; CHECK-NEXT: vldr d16, [r2]301; CHECK-NEXT: vldr d17, [r1]302; CHECK-NEXT: vld1.64 {d0, d1}, [r0]303; CHECK-NEXT: vabal.u32 q0, d17, d16304; CHECK-NEXT: bx lr305 %tmp1 = load <2 x i64>, ptr %A306 %tmp2 = load <2 x i32>, ptr %B307 %tmp3 = load <2 x i32>, ptr %C308 %tmp4 = call <2 x i32> @llvm.arm.neon.vabdu.v2i32(<2 x i32> %tmp2, <2 x i32> %tmp3)309 %tmp5 = zext <2 x i32> %tmp4 to <2 x i64>310 %tmp6 = add <2 x i64> %tmp1, %tmp5311 ret <2 x i64> %tmp6312}313