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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc -mtriple=armv7a-eabihf -mattr=+neon %s -o - | FileCheck %s3 4define <8 x i8> @vabds8(ptr %A, ptr %B) nounwind {5; CHECK-LABEL: vabds8:6; CHECK: @ %bb.0:7; CHECK-NEXT: vldr d16, [r1]8; CHECK-NEXT: vldr d17, [r0]9; CHECK-NEXT: vabd.s8 d0, d17, d1610; CHECK-NEXT: bx lr11 %tmp1 = load <8 x i8>, ptr %A12 %tmp2 = load <8 x i8>, ptr %B13 %tmp3 = call <8 x i8> @llvm.arm.neon.vabds.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)14 ret <8 x i8> %tmp315}16 17define <4 x i16> @vabds16(ptr %A, ptr %B) nounwind {18; CHECK-LABEL: vabds16:19; CHECK: @ %bb.0:20; CHECK-NEXT: vldr d16, [r1]21; CHECK-NEXT: vldr d17, [r0]22; CHECK-NEXT: vabd.s16 d0, d17, d1623; CHECK-NEXT: bx lr24 %tmp1 = load <4 x i16>, ptr %A25 %tmp2 = load <4 x i16>, ptr %B26 %tmp3 = call <4 x i16> @llvm.arm.neon.vabds.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)27 ret <4 x i16> %tmp328}29 30define <2 x i32> @vabds32(ptr %A, ptr %B) nounwind {31; CHECK-LABEL: vabds32:32; CHECK: @ %bb.0:33; CHECK-NEXT: vldr d16, [r1]34; CHECK-NEXT: vldr d17, [r0]35; CHECK-NEXT: vabd.s32 d0, d17, d1636; CHECK-NEXT: bx lr37 %tmp1 = load <2 x i32>, ptr %A38 %tmp2 = load <2 x i32>, ptr %B39 %tmp3 = call <2 x i32> @llvm.arm.neon.vabds.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)40 ret <2 x i32> %tmp341}42 43define <8 x i8> @vabdu8(ptr %A, ptr %B) nounwind {44; CHECK-LABEL: vabdu8:45; CHECK: @ %bb.0:46; CHECK-NEXT: vldr d16, [r1]47; CHECK-NEXT: vldr d17, [r0]48; CHECK-NEXT: vabd.u8 d0, d17, d1649; CHECK-NEXT: bx lr50 %tmp1 = load <8 x i8>, ptr %A51 %tmp2 = load <8 x i8>, ptr %B52 %tmp3 = call <8 x i8> @llvm.arm.neon.vabdu.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)53 ret <8 x i8> %tmp354}55 56define <4 x i16> @vabdu16(ptr %A, ptr %B) nounwind {57; CHECK-LABEL: vabdu16:58; CHECK: @ %bb.0:59; CHECK-NEXT: vldr d16, [r1]60; CHECK-NEXT: vldr d17, [r0]61; CHECK-NEXT: vabd.u16 d0, d17, d1662; CHECK-NEXT: bx lr63 %tmp1 = load <4 x i16>, ptr %A64 %tmp2 = load <4 x i16>, ptr %B65 %tmp3 = call <4 x i16> @llvm.arm.neon.vabdu.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)66 ret <4 x i16> %tmp367}68 69define <2 x i32> @vabdu32(ptr %A, ptr %B) nounwind {70; CHECK-LABEL: vabdu32:71; CHECK: @ %bb.0:72; CHECK-NEXT: vldr d16, [r1]73; CHECK-NEXT: vldr d17, [r0]74; CHECK-NEXT: vabd.u32 d0, d17, d1675; CHECK-NEXT: bx lr76 %tmp1 = load <2 x i32>, ptr %A77 %tmp2 = load <2 x i32>, ptr %B78 %tmp3 = call <2 x i32> @llvm.arm.neon.vabdu.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)79 ret <2 x i32> %tmp380}81 82define <2 x float> @vabdf32(ptr %A, ptr %B) nounwind {83; CHECK-LABEL: vabdf32:84; CHECK: @ %bb.0:85; CHECK-NEXT: vldr d16, [r1]86; CHECK-NEXT: vldr d17, [r0]87; CHECK-NEXT: vabd.f32 d0, d17, d1688; CHECK-NEXT: bx lr89 %tmp1 = load <2 x float>, ptr %A90 %tmp2 = load <2 x float>, ptr %B91 %tmp3 = call <2 x float> @llvm.arm.neon.vabds.v2f32(<2 x float> %tmp1, <2 x float> %tmp2)92 ret <2 x float> %tmp393}94 95define <16 x i8> @vabdQs8(ptr %A, ptr %B) nounwind {96; CHECK-LABEL: vabdQs8:97; CHECK: @ %bb.0:98; CHECK-NEXT: vld1.64 {d16, d17}, [r1]99; CHECK-NEXT: vld1.64 {d18, d19}, [r0]100; CHECK-NEXT: vabd.s8 q0, q9, q8101; CHECK-NEXT: bx lr102 %tmp1 = load <16 x i8>, ptr %A103 %tmp2 = load <16 x i8>, ptr %B104 %tmp3 = call <16 x i8> @llvm.arm.neon.vabds.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)105 ret <16 x i8> %tmp3106}107 108define <8 x i16> @vabdQs16(ptr %A, ptr %B) nounwind {109; CHECK-LABEL: vabdQs16:110; CHECK: @ %bb.0:111; CHECK-NEXT: vld1.64 {d16, d17}, [r1]112; CHECK-NEXT: vld1.64 {d18, d19}, [r0]113; CHECK-NEXT: vabd.s16 q0, q9, q8114; CHECK-NEXT: bx lr115 %tmp1 = load <8 x i16>, ptr %A116 %tmp2 = load <8 x i16>, ptr %B117 %tmp3 = call <8 x i16> @llvm.arm.neon.vabds.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)118 ret <8 x i16> %tmp3119}120 121define <4 x i32> @vabdQs32(ptr %A, ptr %B) nounwind {122; CHECK-LABEL: vabdQs32:123; CHECK: @ %bb.0:124; CHECK-NEXT: vld1.64 {d16, d17}, [r1]125; CHECK-NEXT: vld1.64 {d18, d19}, [r0]126; CHECK-NEXT: vabd.s32 q0, q9, q8127; CHECK-NEXT: bx lr128 %tmp1 = load <4 x i32>, ptr %A129 %tmp2 = load <4 x i32>, ptr %B130 %tmp3 = call <4 x i32> @llvm.arm.neon.vabds.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)131 ret <4 x i32> %tmp3132}133 134define <16 x i8> @vabdQu8(ptr %A, ptr %B) nounwind {135; CHECK-LABEL: vabdQu8:136; CHECK: @ %bb.0:137; CHECK-NEXT: vld1.64 {d16, d17}, [r1]138; CHECK-NEXT: vld1.64 {d18, d19}, [r0]139; CHECK-NEXT: vabd.u8 q0, q9, q8140; CHECK-NEXT: bx lr141 %tmp1 = load <16 x i8>, ptr %A142 %tmp2 = load <16 x i8>, ptr %B143 %tmp3 = call <16 x i8> @llvm.arm.neon.vabdu.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)144 ret <16 x i8> %tmp3145}146 147define <8 x i16> @vabdQu16(ptr %A, ptr %B) nounwind {148; CHECK-LABEL: vabdQu16:149; CHECK: @ %bb.0:150; CHECK-NEXT: vld1.64 {d16, d17}, [r1]151; CHECK-NEXT: vld1.64 {d18, d19}, [r0]152; CHECK-NEXT: vabd.u16 q0, q9, q8153; CHECK-NEXT: bx lr154 %tmp1 = load <8 x i16>, ptr %A155 %tmp2 = load <8 x i16>, ptr %B156 %tmp3 = call <8 x i16> @llvm.arm.neon.vabdu.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)157 ret <8 x i16> %tmp3158}159 160define <4 x i32> @vabdQu32(ptr %A, ptr %B) nounwind {161; CHECK-LABEL: vabdQu32:162; CHECK: @ %bb.0:163; CHECK-NEXT: vld1.64 {d16, d17}, [r1]164; CHECK-NEXT: vld1.64 {d18, d19}, [r0]165; CHECK-NEXT: vabd.u32 q0, q9, q8166; CHECK-NEXT: bx lr167 %tmp1 = load <4 x i32>, ptr %A168 %tmp2 = load <4 x i32>, ptr %B169 %tmp3 = call <4 x i32> @llvm.arm.neon.vabdu.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)170 ret <4 x i32> %tmp3171}172 173define <4 x float> @vabdQf32(ptr %A, ptr %B) nounwind {174; CHECK-LABEL: vabdQf32:175; CHECK: @ %bb.0:176; CHECK-NEXT: vld1.64 {d16, d17}, [r1]177; CHECK-NEXT: vld1.64 {d18, d19}, [r0]178; CHECK-NEXT: vabd.f32 q0, q9, q8179; CHECK-NEXT: bx lr180 %tmp1 = load <4 x float>, ptr %A181 %tmp2 = load <4 x float>, ptr %B182 %tmp3 = call <4 x float> @llvm.arm.neon.vabds.v4f32(<4 x float> %tmp1, <4 x float> %tmp2)183 ret <4 x float> %tmp3184}185 186declare <8 x i8> @llvm.arm.neon.vabds.v8i8(<8 x i8>, <8 x i8>) nounwind readnone187declare <4 x i16> @llvm.arm.neon.vabds.v4i16(<4 x i16>, <4 x i16>) nounwind readnone188declare <2 x i32> @llvm.arm.neon.vabds.v2i32(<2 x i32>, <2 x i32>) nounwind readnone189 190declare <8 x i8> @llvm.arm.neon.vabdu.v8i8(<8 x i8>, <8 x i8>) nounwind readnone191declare <4 x i16> @llvm.arm.neon.vabdu.v4i16(<4 x i16>, <4 x i16>) nounwind readnone192declare <2 x i32> @llvm.arm.neon.vabdu.v2i32(<2 x i32>, <2 x i32>) nounwind readnone193 194declare <2 x float> @llvm.arm.neon.vabds.v2f32(<2 x float>, <2 x float>) nounwind readnone195 196declare <16 x i8> @llvm.arm.neon.vabds.v16i8(<16 x i8>, <16 x i8>) nounwind readnone197declare <8 x i16> @llvm.arm.neon.vabds.v8i16(<8 x i16>, <8 x i16>) nounwind readnone198declare <4 x i32> @llvm.arm.neon.vabds.v4i32(<4 x i32>, <4 x i32>) nounwind readnone199 200declare <16 x i8> @llvm.arm.neon.vabdu.v16i8(<16 x i8>, <16 x i8>) nounwind readnone201declare <8 x i16> @llvm.arm.neon.vabdu.v8i16(<8 x i16>, <8 x i16>) nounwind readnone202declare <4 x i32> @llvm.arm.neon.vabdu.v4i32(<4 x i32>, <4 x i32>) nounwind readnone203 204declare <4 x float> @llvm.arm.neon.vabds.v4f32(<4 x float>, <4 x float>) nounwind readnone205 206define <8 x i16> @vabdls8(ptr %A, ptr %B) nounwind {207; CHECK-LABEL: vabdls8:208; CHECK: @ %bb.0:209; CHECK-NEXT: vldr d16, [r1]210; CHECK-NEXT: vldr d17, [r0]211; CHECK-NEXT: vabdl.s8 q0, d17, d16212; CHECK-NEXT: bx lr213 %tmp1 = load <8 x i8>, ptr %A214 %tmp2 = load <8 x i8>, ptr %B215 %tmp3 = call <8 x i8> @llvm.arm.neon.vabds.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)216 %tmp4 = zext <8 x i8> %tmp3 to <8 x i16>217 ret <8 x i16> %tmp4218}219 220define <4 x i32> @vabdls16(ptr %A, ptr %B) nounwind {221; CHECK-LABEL: vabdls16:222; CHECK: @ %bb.0:223; CHECK-NEXT: vldr d16, [r1]224; CHECK-NEXT: vldr d17, [r0]225; CHECK-NEXT: vabdl.s16 q0, d17, d16226; CHECK-NEXT: bx lr227 %tmp1 = load <4 x i16>, ptr %A228 %tmp2 = load <4 x i16>, ptr %B229 %tmp3 = call <4 x i16> @llvm.arm.neon.vabds.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)230 %tmp4 = zext <4 x i16> %tmp3 to <4 x i32>231 ret <4 x i32> %tmp4232}233 234define <2 x i64> @vabdls32(ptr %A, ptr %B) nounwind {235; CHECK-LABEL: vabdls32:236; CHECK: @ %bb.0:237; CHECK-NEXT: vldr d16, [r1]238; CHECK-NEXT: vldr d17, [r0]239; CHECK-NEXT: vabdl.s32 q0, d17, d16240; CHECK-NEXT: bx lr241 %tmp1 = load <2 x i32>, ptr %A242 %tmp2 = load <2 x i32>, ptr %B243 %tmp3 = call <2 x i32> @llvm.arm.neon.vabds.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)244 %tmp4 = zext <2 x i32> %tmp3 to <2 x i64>245 ret <2 x i64> %tmp4246}247 248define <8 x i16> @vabdlu8(ptr %A, ptr %B) nounwind {249; CHECK-LABEL: vabdlu8:250; CHECK: @ %bb.0:251; CHECK-NEXT: vldr d16, [r1]252; CHECK-NEXT: vldr d17, [r0]253; CHECK-NEXT: vabdl.u8 q0, d17, d16254; CHECK-NEXT: bx lr255 %tmp1 = load <8 x i8>, ptr %A256 %tmp2 = load <8 x i8>, ptr %B257 %tmp3 = call <8 x i8> @llvm.arm.neon.vabdu.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)258 %tmp4 = zext <8 x i8> %tmp3 to <8 x i16>259 ret <8 x i16> %tmp4260}261 262define <4 x i32> @vabdlu16(ptr %A, ptr %B) nounwind {263; CHECK-LABEL: vabdlu16:264; CHECK: @ %bb.0:265; CHECK-NEXT: vldr d16, [r1]266; CHECK-NEXT: vldr d17, [r0]267; CHECK-NEXT: vabdl.u16 q0, d17, d16268; CHECK-NEXT: bx lr269 %tmp1 = load <4 x i16>, ptr %A270 %tmp2 = load <4 x i16>, ptr %B271 %tmp3 = call <4 x i16> @llvm.arm.neon.vabdu.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)272 %tmp4 = zext <4 x i16> %tmp3 to <4 x i32>273 ret <4 x i32> %tmp4274}275 276define <2 x i64> @vabdlu32(ptr %A, ptr %B) nounwind {277; CHECK-LABEL: vabdlu32:278; CHECK: @ %bb.0:279; CHECK-NEXT: vldr d16, [r1]280; CHECK-NEXT: vldr d17, [r0]281; CHECK-NEXT: vabdl.u32 q0, d17, d16282; CHECK-NEXT: bx lr283 %tmp1 = load <2 x i32>, ptr %A284 %tmp2 = load <2 x i32>, ptr %B285 %tmp3 = call <2 x i32> @llvm.arm.neon.vabdu.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)286 %tmp4 = zext <2 x i32> %tmp3 to <2 x i64>287 ret <2 x i64> %tmp4288}289